MSM6688

OKI Semiconductor MSM6688/6688L ADPCM Solid-State Recorder IC FEDL6688-6688L-04 Issue Date: Mar 12. 2002 GENERAL DESCRIPTION The MSM6688/6688L is a “solid-state recorder” IC developed using the ADPCM method. By externally connecting a microphone, a speaker, a speaker drive amplifier, and a dedicated register to store ADPCM data, it can record and play back voice data in a manner similar to a tape recorder. The MSM6688 supports 5 V operation and has a stand-alone mode and a microcontroller interface mode. The MSM6688L supports 3 V operation and controls recording/playback in microcontroller interface mode. In the stand-alone mode, recording/playback conditions can be selected by pins and the MSM6688/6688L can be controlled by a simple drive timing. In the microcontroller interface mode, recording/playback can be controlled by commands from the microcontroller. In the microcontroller interface mode, the MSM6688/6688L is much more flexible than in the stand-alone mode. In addition, the MSM6688/6688L can form easily a recording and playback circuit with fixed messages by connecting serial registers and serial voice ROMs as external memories. Note: This data sheet explains a stand-alone mode and a microcontroller interface mode, separately. Differences between MSM6688 and MSM6688L Parameter Operating voltage Control mode Full scale of A/D and D/A converters Voice detection level for voice triggered starting External-only register ± VDD 64 MSM6688 3.5 to 5.5 V Standalone mode, Microcontroller interface mode 0 to VDD ,± VDD 32 ,± VDD 16 ± VDD 128 MSM6688L 2.7 to 3.6 V Microcontroller interface mode only 1/4 to 3/4 VDD ,± VDD 64 ,± VDD 32 32M bits (max.) 4M bits (MSM6684B) 8M bits (MSM6685A) 4M bits (max.) 4M bits (MSM66V84B) 1/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L CONTENTS GENERAL DESCRIPTION ................................................................................................................................... 1 Differences between MSM6688 and MSM6688L............................................................................................. 1 (1) STAND-ALONE MODE (FOR MSM6688 (5 V VERSION))...................................................................... 4 FEATURES............................................................................................................................................................. 4 BLOCK DIAGRAM ............................................................................................................................................... 5 PIN CONFIGURATION (TOP VIEW) .................................................................................................................. 6 PIN DESCRIPTIONS ............................................................................................................................................. 7 ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))................................................................. 11 RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version)).............................................. 11 ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))................................................................ 12 TIMING DIAGRAMS .......................................................................................................................................... 16 FUNCTIONAL DESCRIPTION........................................................................................................................... 29 Recording Time and Memory Capacity........................................................................................................... 29 Connection of an Oscillator ............................................................................................................................. 29 Power Supply Wiring....................................................................................................................................... 31 Configuring SGC and SG pins......................................................................................................................... 31 Analog Input Amplifier Circuit ....................................................................................................................... 32 Connection of LPF Circuit Peripherals............................................................................................................ 34 LPF Characteristics.......................................................................................................................................... 35 Reset Function ................................................................................................................................................. 36 Power Down by the PDWN pin...................................................................................................................... 37 Record/Playback Control Mode....................................................................................................................... 38 Deleting phrases............................................................................................................................................... 40 Recording Method ........................................................................................................................................... 41 Playback Method ............................................................................................................................................. 42 ROM Playback Method ................................................................................................................................... 43 Voice Triggered Starting ................................................................................................................................. 44 Method of Temporarily Stopping Record/Playback by Pause Function.......................................................... 46 APPLICATION CIRCUIT.................................................................................................................................... 47 (2) MICROCONTROLLER INTERFACE MODE (FOR MSM6688 (5 V VERSION) AND MSM6688L (3 V VERSION)) ............................................................................................................. 48 FEATURES........................................................................................................................................................... 48 BLOCK DIAGRAM ............................................................................................................................................. 49 PIN CONFIGURATION (TOP VIEW) ................................................................................................................ 50 PIN DESCRIPTIONS ........................................................................................................................................... 51 ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))................................................................. 54 RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version)).............................................. 54 ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))................................................................ 54 ABSOLUTE MAXIMUM RATINGS (for MSM6688L (3 V Version)) .............................................................. 59 RECOMMENDED OPERATING CONDITIONS (for MSM6688L (3 V Version)) ........................................... 59 ELECTRICAL CHARACTERISTICS (for MSM6688L (3 V Version)) ............................................................. 59 TIMING DIAGRAMS .......................................................................................................................................... 64 2/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L FUNCTIONAL DESCRIPTION........................................................................................................................... 83 Recording Time and Memory Capacity........................................................................................................... 83 Connection of an Oscillator ............................................................................................................................. 83 Power Supply Wiring....................................................................................................................................... 86 Configuring SGC and SG pins......................................................................................................................... 86 Analog Input Amplifier Circuit ....................................................................................................................... 87 Connection of LPF Circuit Peripherals............................................................................................................ 89 LPF Characteristics.......................................................................................................................................... 89 Full Scale of A/D and D/A Converters ............................................................................................................ 90 Reset Function ................................................................................................................................................. 91 Power Down by the PDWN pin...................................................................................................................... 92 Record/Playback Control Modes ..................................................................................................................... 93 Data Configuration of External Serial Registers.............................................................................................. 95 Data Configuration of External Serial Voice ROMs ..................................................................................... 104 Command Description ................................................................................................................................... 106 Status Register ............................................................................................................................................... 115 Inputting the Commands................................................................................................................................ 118 Changes of Record/Playback Conditions....................................................................................................... 122 Setting and Confirming the Record/Playback Conditions ............................................................................. 123 Flex Record/Playback Method....................................................................................................................... 134 Direct Record/Playback Method.................................................................................................................... 141 ROM Playback by Inputting Address Code................................................................................................... 144 Direct ROM Playback Method ...................................................................................................................... 148 Stopping Record/Playback Temporarily (by the PAUSE Command) ........................................................... 150 Transferring Data to/from External Memories .............................................................................................. 151 Record/Playback by Inputting/Outputting Voice Data via Data Bus............................................................. 157 Suppression of Pop Noise at AOUT Output (by the LEV Command) .......................................................... 161 APPLICATION CIRCUIT.................................................................................................................................. 163 PACKAGE DIMENSIONS................................................................................................................................. 164 REVISION HISTORY ........................................................................................................................................ 166 3/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L (1) STAND-ALONE MODE (FOR MSM6688 (5 V VERSION)) FEATURES • • • • • • 3-bit or 4-bit ADPCM Built-in 12-bit AD converter Built-in12-bit DA converter Built-in microphone amplifier Built-in low-pass filter Attenuation characteristics –40 dB/oct External memories Serial registers, 32M bits maximum (for variable messages) 8M bit serial register (MSM6685A) can be driven directly Serial voice ROMs, 4M bits maximum (for fixed messages) 1M bit serial voice ROM (MSM6595A) can be driven directly 2M bit serial voice ROM (MSM6596A) can be driven directly 3M bit serial voice ROM (MSM6597A) can be driven directly Sampling frequency 4.0 kHz, 5.3 kHz, 6.4 kHz or 8.0 kHz (master clock frequency = 4.096 MHz) 8.0 kHz, 10.6 kHz, 12.8 kHz, or 16.0 kHz (master clock frequency = 8.192 MHz) Number of phrases 63 phrases for variable messages 63 phrases for fixed messages Maximum recording time (when external 32M bit RAM is connected) 34 minutes (for 16 kbps ADPCM) 23 minutes (for 24 kbps ADPCM) 17 minutes (for 32 kbps ADPCM) Voice triggered starting function Pause function Master clock frequency: 4.096 to 8.192 MHz Power supply voltage: Single 5 V power supply Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (MSM6688GS-2K) • • • • • • • • 4/167 OKI Semiconductor DEL ST SP PAUSE CA0 CA1 CA2 CA3 CA4 CA5 TEST TEST BLOCK DIAGRAM MCUM Phrase Register Test Circuit RESET PDWN PDMD Data I/O Address Controller DI/O DROM RSEL1 RSEL2 SADX SADY TAS RWCK WE Register Controller CS1 CS2 CS3 CS4 Timing VDS ROM SAM1 SAM2 Controller MON NAR XT XT ADPCM Analyzer/Synthesizer OSC REC/PLA 4B/3B Latch MIN LPF 12-bit ADC – DVDD 12-bit DAC DVDD’ AVDD DGND AGND AOUT FOUT ADIN SG SGC + SG Circuit MOUT LIN – + FEDL6688-6688L-04 MSM6688/6688L LOUT AMON FIN 5/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L PIN CONFIGURATION (TOP VIEW) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 REC/PLAY ST SP RESET NAR MON RWCK DVDD XT XT WE DROM DI/0 CS4 CA0 CA1 CA2 CA3 CA4 CA5 DEL PAUSE PDMD MCUM SAM1 SAM2 4B/3B VDS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CS3 CS2 CS1 SADX SADY TAS SAS PDWN TEST TEST RSEL2 RSEL1 DGND AGND ROM ADIN FOUT AOUT FIN AMON DVDD’ AVDD SG SGC LOUT LIN MOUT MIN 56-Pin Plastic QFP 6/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L PIN DESCRIPTIONS Pin 49 21 22 30 29 23 24 28 26 27 25 20 19 17 16 18 39 38 Symbol DVDD DVDD’ AVDD DGND AGND SG SGC MIN LIN MOUT LOUT AMON FIN FOUT ADIN AOUT SADX SADY Type — — — — — O I O O I O I O Description Digital power supply pin. Insert a bypass capacitor of 0.1 µF or more between this pin and the DGND pin. Digital power supply pin Analog power supply pin. Insert a bypass capacitor of 0.1 µF or more between this pin and the AGND pin. Digital ground pin Analog ground pin Output pin for analog circuit reference voltage (signal ground) Inverting input pin of the built-in OP amplifier. Non-inverting input pin is internally connected to SG (signal ground). MOUT and LOUT are output pins of the built-in OP amplifier for MIN and LIN, respectively. This pin is connected to the LOUT pin in the recording mode and to the DA converter output in the playback mode. Used to connect the built-in LPF input (FIN pin). Input pin of built-in LPF Output pin of built-in LPF. Used to connect the AD converter input (ADIN pin). Input pin of the built-in 12-bit AD converter Output pin of the built-in LPF. This pin outputs playback waveforms and used to connect an external speaker drive amplifier. (Serial Address Data). SADX is used to connect the SAD pin of each external serial register and the SADX pin of each external serial voice ROM. SADY is used to connect the SADY pin of each external serial voice ROM. Outputs of starting address of read/write. (Serial Address Strobe). Used to connect the SAS pin of external serial register and the SASX and SASY pins of external serial voice ROM. Clock pin to write the serial address. (Transfer Address Strobe). Used to connect the TAS pin of each external serial register and serial voice ROM. This pin outputs address strobe outputs to set the serial address data from the SADX and SADY pins into the internal address counter of each serial register and serial voice ROM. (Read/Write Clock). Used to connect the RWCK pin of each external serial register and the RDCK pin of each external serial voice ROM. This pin outputs a clock to read data from or write it into each external serial register. (Write Enable). Used to connect the WE pin of each external serial register. This pin outputs WE signal to select either read or write mode. O 36 SAS O 37 TAS O 50 RWCK O 46 WE O 7/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Pin 44 45 40 41 42 43 Symbol DI/O DROM CS1 CS2 CS3 CS4 Type I/O I Description (Data I/O) Used to connect the DIN and DOUT pins of DRAM and serial register. This pin outputs the data to be written into the serial register or inputs the data read from the serial registers. (Data ROM) Used to connect the DOUT pin of each external serial voice ROM. (Chip Select) Used to connect the CS pin of serial register and the CS (CS1, CS2, CS3) pins of each serial voice ROM. (Register Select) These are used to select the number of external serial registers. O 31 32 RSEL1 RSEL2 I RSEL2 RSEL1 Number of serial registers L L 1 L H 2 H L 3 H H 4 10 MCUM I This pin is used to select either the stand-alone mode or the microcontroller interface mode. Low level: Stand-alone mode High level: Microcontroller interface mode A high input level at this pin causes the MSM6688 to be initialized and to go into the power down state. (Power Down) When a low level is input to this pin, the MSM6688 goes to the power down state. Unlike the RESET pin, this pin does not force to reset the MSM6688. When an low level is applied to this PDWN pin during recording operation, the MSM6688 is halted, and will be maintained in the power down state while PDWN is low. After this pin is restored to a high level, postprocessing for recording will be performed. Used to connect an oscillator. When an external clock is used, input the clock through this pin. At the power down state, this pin must be set to the ground level. Used to connect an oscillator. When an external clock is used, this pin must be left open. Used to test the MSM6688. Input a low level to the TEST pin and a high level to the TEST pin. 53 RESET I 35 PDWN I 47 48 34 33 XT XT TEST TEST I O I 8/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Pin 15 56 55 54 8 Symbol ROM REC/PLAY ST SP PAUSE Type I I I I I Description When low, selects the record/playback operation. When high, selects the ROM playback operation. Used to select the recording mode or the playback mode. This pin is invalid during the ROM playback operation. When low, selects the playback mode. When high, selects the recording mode. When a low-level pulse is applied to this pin, the record/playback or ROM playback is started. When a low-level pulse is applied to this pin, the record/playback or ROM playback is started. When a low-level pulse is applied to this pin, the record/playback or ROM operation is stopped temporarily. When a low level pulse is applied to this pin, all phrase deletion or specified phrase deletion can be performed according to the setting of pins CA0 through CA5, ch00: All phrase deletion ch01 to ch3F: Specified phrase deletion After powering up, be sure to input RESET signal and then to delete all phrases. After completing this procedure, start the record/playback operation. Input pins used to specify desired phrases. A total of 63 phrases can be specified independently for record/playback operation and the ROM playback operation. CA5 CA4 L L L … H H CA3 L L L … H H CA2 L L L … H H CA1 L L H … H H CA0 L H L … L H Phrase No. ch00 ch01 ch02 … ch3E ch3F Remarks All phrase deletion A total of 63 phrases can be used both for record/playback and ROM playback operation. 7 DEL I 1-6 CA0-CA5 I L L L H H … 13 4B/3B I Input pin used to select one of two types of ADPCM bit length. When low, selects the 3-bit ADPCM. When high, selects the 4-bit ADPCM. 9/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Pin Symbol Type Description Used to select one of the following four types of sampling frequency. The relationship between the master clock frequency (fOSC) and the sampling frequency (fSAMP) is shown below. Values in parentheses denote the sampling frequencies for fOSC = 4.096 MHz. 11 12 SAM1 SAM2 I SAM2 SAM1 fSAMP L L fOSC 1024 (4.0 kHz) L H fOSC 768 (5.3 kHz) H L fOSC 640 (6.4 kHz) H H fOSC 512 (8.0 kHz) 9 PDMD I This input pin is used to select the condition for transition to the power-down state. Low level: The MSM6688 automatically goes to the power-down state, excepting the time the record/playback operation is being performed. High level: The MSM6688 automatically goes to the standby state, instead of the power-down state, excepting the time the record/playback operation is being performed. In this case, the MSM6688 can be placed in the power-down state by setting the REST pin to a high level. If it is desired to use the built-in LPF for an external circuit, this standby mode must be selected by applying a high level to the PDMD pin. Used to select the voice triggered starting that starts recording when the voice input exceeds the preset amplitude. A high input level on this pin enables the voice triggered starting circuit. Outputs a high level while the record/playback operation is being performed. Output pin to indicate the enable or disable state of the operation for specifying a phrase. When continuous ROM playback is performed, the next phrase can be specified after verifying that the NAR pin becomes high. 14 51 52 VDS MON NAR I O O 10/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version)) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG Condition Ta = 25°C Ta = 25°C — Rating –0.3 to +7.0 –0.3 to VDD+0.3 –55 to +150 Unit V V °C RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version)) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition DGND = AGND = 0 V — — Range 3.5 to 5.5 (Note 1) –40 to +85 4.0 to 8.192 Unit V °C MHz Note: 1. Recording and playback should be performed at a power supply voltage of 4.5 to 5.5 V. For other operations such as backup for a serial register, the IC operates at 3.5 to 5.5 V. 11/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version)) DC Characteristics DVDD = DVDD’ = AVDD = 4.5 to 5.5 V (Note 5) DGND = AGND = 0 V, Ta = –40 to +85°C Parameter High input voltage Low input voltage High output voltage Low output voltage High input current (Note 1) High input current (Note 2) Low input current (Note 3) Low input current (Note 2) Low input current (Note 4) Operating current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IIL3 IDD Condition — — IOH = –40 µA IOL = 2 mA VIH = VDD VIH = VDD VIL = GND VIL = GND VIL = GND fOSC = 8 MHz, no load During power down, no load Standby current Consumption IDDS Ta = –40 to +70°C During power down, no load Ta = –40 to +85°C — — 50 µA Min. 0.8 × VDD — VDD – 0.3 — — — –10 –20 –400 — Typ. — — — — — — — — — 15 Max. — 0.2 × VDD — 0.45 10 20 — — –20 30 Unit V V V V µA µA µA µA µA mA — — 10 µA Notes: 1. 2. 3. 4. Applies to all input pins excluding the XT pin. Applies to the XT pin. Applies to the all input pins without pull-up resistors, excluding the XT pin. Applies to the input pins (ST, SP, PAUSE, DEL) with pull-up resistors, excluding the XT pin. 12/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Analog Characteristics DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C Parameter DA output relative error FIN admissible input voltage range FIN input impedance ADIN admissible input voltage range ADIN input impedance Op-amp open loop gain Op-amp input impedance Op-amp load resistance AOUT load resistance FOUT load resistance Symbol |VDAE| VFIN RFIN VADIN RADIN GOP RINA ROUTA RAOUT RFOUT Condition No load — — — — fIN = 0 to 4 kHz — — — — Min. — 1 1 0 1 40 1 200 50 50 Typ. — — — — — — — — — — Max. — VDD –1 — VDD — — — — — — Unit mV V MΩ V MΩ dB MΩ kΩ kΩ kΩ 13/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L AC Characteristics DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter RESET pulse width RESET execution time PDWN low level time PDWN high level time Oscillating time after input of PDWN BUSY time after release of PDWN ST pulse width ST pulse width PAUSE pulse width DEL pulse width Time required to delete all phrases Time required to delete a specified phrase Time from input of DEL pulse to CSI fall (Note 1)* * (Note 1)* * (Note 1)* (Note 2)** ** ** (Note 2)* * * (Note 2) * Symbol tRST tREX tPDL tPDH tPX tBPD tST tSP tPSE tDEL tWBLA tWBL1 tDCS tCAH tAD1 tSTN tMID tTMH1 tTMH2 tTMH3 tPMH1 tPMH2 tPMH3 tSTVH tSPVH Min. 1 — 500 500 125 0.25 40 40 40 40 550 70 — 1 — — 0.75 — — — — — — — — Typ. — 1 — — — — — — — — — — — — 1 — — — — — — — — — — Max. — — — — 500 — — — — — — — 270 — — 40 1 50 20 1 80 2 2 50 80 Unit µs ms µs µs µs ms µs µs µs µs ms ms µs ms ms µs ms ms ms ms ms ms ms ms ms Hold time of CA0 to CA5, REC/PLAY after MON rise Address control time at the start of record/playback * Time from input of ST pulse to NAR fall (Note 2)* * * * * * Unvoiced time between phrases during repeated playback Time from input of ST pulse to MON rise Time from input of SP pulse to MON fall Record Playback Record Playback ROM playback * POMD =H ROM playback * Time from input of ST pulse to standby for voice * Time from input of SP pulse during standby for voice to release of standby for voice * Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. Note: 1. The oscillation start stabilization time is added to tREX and tBPD. The oscillation start stabilization time is several tens of milliseconds for crystals and several hundreds of microseconds for ceramic oscillators. Note: 2. The oscillation start stabilization time is added if PDMD pin = “L”. The oscillation start stabilization time is several tens of milliseconds for crystals and several hundreds of microseconds for ceramic oscillators. 14/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter Time from input of ST pulse to MON rise Time from input of SP pulse to MON fall POMD =L Record Playback Record Playback * * * * Symbol tTML1 tTML2 tTML3 tPML1 tPML2 tPML3 tSTVL tSPVL tAOR tAOF tPP tPST Min. — — — — — — — — — — — — Typ. — — — — — — — — 64 256 — — Max. 120 150 150 80 260 260 120 80 — — 1 1 Unit ms ms ms ms ms ms ms ms ms ms ms ms ROM playback * ROM playback * Time from input of ST pulse to standby for voice * Time from input of SP pulse during standby for voice to release of standby for voice * Standby transition time at start of playback Standby transition time at end of playback * * ** Time from input of PAUSE pulse to pause Time from input of ST pulse during pause to restart of record/playback ** Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. 15/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L TIMING DIAGRAMS Reset Function VDD tRST RESET (I) tREX Undefined Power down Standby for record/playback Reset operation in progress Power Down by PDWN Pin tPDL PDWN (I) tPDH tPX Note 1 XT (I) X T (O ) Oscillation in progress Oscillation in progress tBPD Power down Postprocessing Standby Note: 1. When an external clock is used, continue to apply the clock input to the XT terminal during tPX after the PDWN pin is set to a low level. 16/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Timing for Deletion of All Phrases CA0-CA5 (I) tDEL D E L (I ) tWBLA tDCS CSI (O) Standby Deletion of all phrases Standby Timing for Deletion of a Specified Phrase CA0-CA5 (I) tDEL D E L (I ) tWBL1 tDCS CSI (O) Standby Deletion of a specified phrase Standby 17/167 OKI Semiconductor Recording Timing (PDMD Pin = High) RESET (I) ROM Bit rate designation (I) SAM1, SAM2 (I) (I) 4B/3B CA0-CA5 (I) Phase designation tST tSP tCAH REC/PLAY (I) ST (I) SP Oscillation in progress tTMH1 (I) XT XT (I) (O) tPMH1 MON tAD1 (O) tSTN NAR (O) Power down Address control Standby Recording in progress Standby Power down FEDL6688-6688L-04 MSM6688/6688L 18/167 Timing for Voice Triggered Recording (PDMD Pin = High) OKI Semiconductor RESET (I) ROM (I) VDS Bit rate designation Phrase designation tST tCAH tSP tSP (I) SAM1, SAM2 (I) (I) 4B/3B CA0-CA5 (I) REC/PLAY (I) ST (I) SP Oscillation in progress tSTVH tSPVH (I) XT XT (I) (O) tPMH1 MON (O) tSTN NAR tAD1 Standby for voice Voice detected Address control (O) Power down Standby Recording Standby When STOP pulse is input during standby for voice, the MSM6688 goes to the recording standby state. Power down FEDL6688-6688L-04 MSM6688/6688L 19/167 Playback Timing (PDMD Pin = High) OKI Semiconductor RESET (I) ROM Bit rate designation (I) SAM1, SAM2 (I) 4B/3B (I) CA0-CA5 (I) Phrase designation REC/PLAY tST tSP tCAH (I) ST (I) SP Oscillation in progress tTMH2 (I) XT XT (I) (O) tPMH2 MON NAR (O) (O) tSTN 1/2 VDD level tAD1 Standby Address control Playback 1/2 VDD level GND level Standby Power down FEDL6688-6688L-04 AOUT (O) GND level Power down MSM6688/6688L 20/167 ROM Playback Timing (PDMD Pin = High) OKI Semiconductor RESET (I) ROM (I) CA0-CA5 (I) Phrase designation tST tCAH tSP ST (I) SP (I) XT XT Oscillation in progress tTMH3 (I) (O) tPMH3 MON (O) tSTN NAR 1/2 VDD level tAD1 Standby Address control (O) 1/2 VDD level GND level Playback Standby Power down FEDL6688-6688L-04 AOUT (O) GND level Power down MSM6688/6688L 21/167 Continuous ROM Playback Timing (PDMD Pin = High) OKI Semiconductor RESET 2nd phrase designation (I) ROM (I) CA0-CA5 (I) 1st phrase designation ST tSP (I) SP Oscillation in progress tTMH3 tPMH3 (I) XT XT (I) (O) MON (O) tSTN NAR (O) 1/2 VDD level tAD1 Standby Address control 1st phrase playback Unvoiced FEDL6688-6688L-04 tMID 2nd phrase playback Standby GND level Power down 1/2 VDD level AOUT (O) GND level Power down MSM6688/6688L 22/167 OKI Semiconductor Recording Timing (PDMD Pin = Low) RESET (I) ROM (I) SAM1, SAM2 (I) (I) 4B/3B Bit rate specifying operation CA0-CA5 (I) Phrase specifying operation REC/PLAY tCAH tSP (I) ST tST (I) SP Oscillation in progress tTML1 (I) XT XT (I) (O) tPML1 MON (O) tSTN NAR tAD1 Address control (O) Power down Analog stable time Recording in progress Power down FEDL6688-6688L-04 MSM6688/6688L 23/167 Timing for Voice Triggered Recording (PDMD Pin = Low) OKI Semiconductor RESET (I) ROM (I) VDS Bit rate designation Phrase designation tCAH tSP tSP (I) SAM1, SAM2 (I) (I) 4B/3B CA0-CA5 (I) REC/PLAY (I) tST ST (I) SP Oscillation in progress tSPVL (I) XT XT (I) (O) tSTVL tPML1 MON (O) tSTN NAR tAD1 Standby for voice Voice detected Address (O) Power down Analog stable time Recording Power down When STOP pulse is input during standby for voice, the MSM6688 goes to the recording standby state. FEDL6688-6688L-04 MSM6688/6688L 24/167 Playback Timing (PDMD Pin = Low) OKI Semiconductor RESET (I) ROM (I) SAM1, SAM2 (I) (I) 4B/3B Bit rate designation CA0-CA5 (I) Phrase designation REC/PLAY tCAH tSP (I) tST ST (I) SP Oscillation in progress tTML2 (I) XT XT (I) (O) tPML2 MON (O) tSTN NAR 1/2 VDD level tAOR tAD1 Address control Standby transition (O) AOUT (O) GND level tAOF Playback Standby transition GND level Power down FEDL6688-6688L-04 Power down MSM6688/6688L Analog stable time 25/167 ROM Playback Timing (PDMD Pin = Low) OKI Semiconductor RESET (I) ROM (I) CA0-CA5 (I) Phrase designation tCAH tSP ST (I) tST SP Oscillation in progress tTML3 (I) XT XT (I) (O) tPML3 MON (O) tSTN NAR 1/2 VDD level tAOR tAD1 Address control Standby transition (O) AOUT (O) GND level tAOF Playback GND l l Power down Standby transition FEDL6688-6688L-04 Power down Analog stable time MSM6688/6688L 26/167 Continuous ROM Playback Timing (PDMD Pin = Low) OKI Semiconductor RESET 2nd phrase designation (I) ROM (I) CA0-CA5 (I) 1st phrase designation ST tSP (I) SP Oscillation in progress tTML3 (I) XT XT (I) (O) tPML3 MON (O) tSTN NAR 1/2 VDD level tAOR tAD1 1st phrase playback Address tl tMID (O) AOUT (O) GND level tAOF 2nd phrase playback Unvoiced Standby transition GND level Power down FEDL6688-6688L-04 Power down Analog stable time Standby transition MSM6688/6688L 27/167 Record/Playback Pause Timing OKI Semiconductor tST tST Restart pulse tSP tPSE Note 1 Start pulse ST (I) SP tPSE (I) PAUSE tPP tPST tPP (I) MON Pause Record/Playback Pause (O) Standby Record/Playback Standby Note 1: This time interval varies depending on the state of PDMD pin and the record/playback mode and is one of tPMH1, tPMH2, tPMH3, tPML1, tPML2 and tPML3. FEDL6688-6688L-04 MSM6688/6688L 28/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L FUNCTIONAL DESCRIPTION Recording Time and Memory Capacity The recording time depends on the memory capacity of the external serial registers, sampling frequency, and ADPCM bit length, and is given by Recording time = 1.024 × memory capacity (K bits) sampling frequency (kHz) × bit length (bits) (seconds) 4096 For example, if the sampling frequency is kHz (= 5.333 kHz), ADPCM bit length is 3 bits, and four 8M 768 bit serial registers are used, the recording time can be obtained as follows. Recording time = = 1.024 × (8192 × 4 – 64) 5.333 × 3 34 minutes 53 seconds = 2093 seconds In the above equation, the memory capacity is obtained by subtracting the memory capacity (64K bits) for the channel index area from the total memory capacity. Connection of an Oscillator Connect a ceramic oscillator or a crystal oscillator to XT and XT pins as shown below. The optimal load capacities when connecting ceramic oscillators from MURATA MFG. and KYOCERA CORPORATION are shown below for reference. MSM6688 XT C1 XT C2 Ceramic oscillator Type CSTLS4M00G53-B0 (with capacitor) MURATA MFG. CSTCR4M00G53-R0 (with capacitor) CSTLS6M00G53-B0 (with capacitor) CSTCR6M00G53-R0 (with capacitor) CSTLS8M00G53-B0 (with capacitor) CSTCC8M00G53-R0 (with capacitor) Freq. (MHz) 4.0 Optimal load capacity C1 (pF) C2 (pF) Power supply voltage (V) Operating temperature (°C) 6.0 — — 3.5 to 5.5 –40 to +85 8.0 29/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Ceramic oscillator Type KBR-4.0MSA KBR-4.0MKS (with capacitor) KYOCERA CORP. PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS (with capacitor) PBRC6.00A PBRC6.00B KBR-8.0M PBRC8.00A PBRC8.00B 8.0 Freq. (MHz) Optimal load capacity C1 (pF) C2 (pF) Power supply voltage (V) Operating temperature (°C) 4.0 6.0 33 33 3.5 to 5.5 –40 to +85 30/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Power Supply Wiring As shown in the following diagram, supply the power to this MSM6688 from the same power source, but separate the power supply wiring to the analog portion from that to the logic position. +5 V DVDD’ DVDD AVDD MSM6688 DGND AGND The following connections are not permitted. Analog power supply Digital power supply DVDD DVDD’ AVDD +5 V DVDD DVDD’ AVDD Configuring SGC and SG pins The internal equivalent circuit around the SGC and SG pins is shown below. AVDD MSM6688 MSM6688L 50 kΩ (TYP) + – 50 kΩ (TYP) SGC To OP amplifier, LPF SG 20 kΩ (TYP) AGND Power-down signal Switch is open at power-down AGND AGND 31/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L The SG signal is a reference voltage (signal ground) for internal OP amplifiers and LPF. Install a capacitor between the SGC pin and AGND and between the SG pin and AGND respectively in order to make the SG signal noiseless. It is recommended to use an approx. 0.1 µF capacitor, which should be determined after evaluating the tone quality. It takes several ten msec until the DC levels such as the SG level of the analog circuit is stabilized after the power-down mode is cancelled. The larger capacitance of a capacitor connected to SGC or SG requires the longer time for stabilizing. After the power-down mode is cancelled, enter voices after the DC levels for the analog circuit has been stabilized. When the device is in power-down mode, the output voltage of the SG pin becomes unstable. Therefore, SG must not be supplied to external circuits. Otherwise, power supply current may be leaked via the internal SG circuit. Same is true for the SGC pin. Analog Input Amplifier Circuit This MSM6688 has two built-in operational amplifiers for amplifying the microphone output. Each OP amplifier is provided with the inverting input pin and output pin. The analog circuit reference voltage SG (signal ground) is connected internally to the non-inverting input of each OP amplifier. For amplification, form an inverting amplifier circuit and adjust the amplification factor by using external resistors as shown below. VIN –+ R1 MIN R2 VMO R3 MOUT – + OP amp 1 R4 R3 R2 • R4 R1 • R3 R4 LIN LOUT VLO VLO VDD VDD–1 1/2VDD 1 GND SG VLO= – + OP amp 2 VMO= VIN(V) During the time the recording operation is performed, the output VLO of OP amp 2 is connected to the input FIN of the built-in LPF. The allowable FIN input voltage (VFIN) ranges from 1 V to (VDD – 1) V. Therefore, the amplification factor must be adjusted so that the VLO amplitude can be within the allowable FIN input voltage range. For example, if VDD = 5 V, VLO becomes 3 Vp-p max. If VLO exceeds the allowable FIN input voltage range, the output of the LPF will be a clipped waveform. The load resistance ROUTA of the OP amplifier is 200 kΩ minimum, so that the feedback resistors R2 and R4 of the inverting amplifier circuit must be 200 kΩ or more. 32/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L When OP amplifier 1 is not used and OP amplifier 2 is used, the MIN pin must be connected to AGND or AVDD, and the MOUT pin must be open. Even if amplification is unnecessary, OP amplifier 2 must be always used. Below is an example of an analog input amplifier circuit when the amplification factor is 1. (200 kΩ) R3 (200 kΩ) R4 Input signal AGND (or AVDD) MIN MOUT – + OP amplifier 1 LIN LOUT – + OP amplifier 2 MSM6688 MSM6688L SG 33/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Connection of LPF Circuit Peripherals The AMON pin is connected internally to the output of the amplifier circuit (LOUT pin) in the recording mode and to the output of the built-in DA converter in the playback mode. Therefore, connect the AMON pin directly to the input (FIN pin) of the built-in LPF. Both the FOUT and AOUT pins are the output pins of the built-in LPF. Connect the FOUT pin to the input (ADIN pin) of the built-in AD converter and connect the AOUT pin to an external speaker through an external speaker drive amplifier. In the MSM6688, the connection of each of the FOUT and AOUT pins is changed to one of the output of the LPF, GND (ground) level, and SG (signal ground) level, depending on the operation status as shown below. When PDMD pin = high level: Analog pin FOUT pin AOUT pin At power down (RESET pin = H) GND level GND level During operation (RESET pin = L) Recording mode LPF output (recording waveform) SG level Playback mode LPF output LPF output (playback waveform) When PDMD pin = L: Analog pin FOUT pin AOUT pin At power down GND level GND level During operation Recording mode LPF output (recording waveform) GND level Playback mode LPF output LPF output (playback waveform) 34/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L When PDMD pin = H: Speaker drive amplifier LIN LOUT AMON FIN AOUT FOUT ADIN – + SG DAC Record mode Playback mode LPF SG Playback mode – + Power down ADC Record mode GND – + Power down GND Note: This diagram shows the state of each switch during the recording operation. When PDMD = L: Speaker drive amplifier LIN LOUT AMON FIN AOUT FOUT ADIN – + SG DAC Record mode Playback mode – + Playback ADC LPF – + Power down GND Note: This diagram shows the state of each switch during the recording operation. LPF Characteristics [dB] 20 10 This IC contains a fourth-order switched-capacitor LPF. 0 The attenuation characteristic of this LPF is –40 dB/oct. –10 The cut-off frequency and frequency characteristics of –20 this LPF vary in proportion to the sampling frequency –30 (fSAMP). The cut-off frequency is preset to 0.4 times –40 the sampling frequency. The following graph depicts the –50 frequency characteristics of the LPF at fSAMP = 8 kHz. –60 –70 –80 100 1K 10K [Hz] LPF Frequency Characteristics (fSAMP = 8.0 kHz) 35/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Reset Function By applying a high level to the RESET pin, the MSM6688 stops frequency oscillation to minimize current consumption and goes to the power-down state. At the same time, the control circuit is reset and initialized. If a high level is applied to the RESET pin during record/playback operation, the MSM6688 is set to the power-down state and initialized state, so that voice data becomes undefined. The following shows the power-down state of the MSM6688. (1) Frequency oscillation is stopped and all operations of the internal circuit are halted. (2) The current consumption is minimized. When an external clock is used, apply a ground (GND) level to the XT pin at power down so that no current can flow into the oscillation circuit. (3) CS1-CS4 pins are set to a high level to minimize the current consumption of external serial registers and serial voice ROMs. (4) Pull-up resistors are removed from the input control ST, SP, PAUSE, and DEL pins. (5) The state of the output pins are as follows. Pin name SAS, TAS, CS1-CS4, RWCK SADX, WE, NAR SADY “L” level AOUT, FOUT Power down mode with RESET = “H” “H” level “H” level “L” level “L” level GND level Power down mode with PDWN = “L” “H” level “H” level or “L” level “H” level or “L” level “L” level GND level After powering up the MSM6688, be sure to initialize it by applying a high level to the RESET pin. 36/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Power Down by the PDWN pin By applying a low level to the PDWN pin, the MSM6688 may be set to the power-down state, in which the oscillation and all operations of internal circuits are halted. Unlike the reset operation by the RESET input, the control circuit will not be initialized by this power-down operation. The power-down operation will not affect the data in the internal control circuit and external serial registers. Therefore, this power-down operation is useful when the battery backup takes place in case of power failure. When PDWN becomes low during one of the following operations, their respective operations will be performed after the power-down state is released (PDWN = H). (1) When the MSM6688 is powered down (PDWN = L) during the record/plaback operation: The record/playback operation is stopped. After the release of the power-down state, the postprocessing will be performed. (2) When the MSM6688 is powered down (PDWN = L) during the phrase deleting operation: The phrase deleting operation is temporarily stopped and will be restarted after the release of the power-down state. (3) When the MSM6688 is powered down (PDWN = L) during the time the transition of the AOUT output to a DC level is in progress: This transition operation is temporalily stopped and will be continued after the release of the power-down state. 37/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Record/Playback Control Mode Either record/playback mode or ROM playback mode can be selected through the ROM pin as described below. ROM pin L H Record/playback control mode Record/playback ROM playback 1. Record/playback The recorded voice data is stored in serial registers. The recording area is indirectly allocated to each phrase by setting the phase specifying pins CA0 to CA5 (63 phrases). The recording area for each phrase is managed by the MSM6688 as described below. The total memory capacity of the connected external serial registers is equally divided into 256 memory blocks. When recording is performed, voice data is written into the memory blocks unused by other phrases. When a specified phase is deleted, the blocks used by this phrase become unused blocks. When re-recording is performed, voice data is written in the memory area consisting of the memory blocks used by this phrase and the unused memory blocks. The memory capacity of one memory block and the number of initially available memory blocks (recording time) vary according to the total memory capacity of the connected serial registers. RSEL2 RSEL1 Total memory capacity Memory capacity of one block Recording time of one block 16 kbps 24 kbps 32 kbps L L 8M bits 32K bits 2.0 seconds 1.4 seconds 1.0 seconds 254 L H 16M bits 64K bits 4.1 seconds 2.7 seconds 2.0 seconds 255 H L 24M bits 128K bits 8.2 seconds 5.5 seconds 4.1 seconds 191 H H 32M bits 128K bits 8.2 seconds 5.5 seconds 4.1 seconds 255 Number of initially available blocks 38/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. ROM playback For playback of the voice data stored in the connected serial voice ROM, the playback area is allocated indirectly to each fixed message phrase by setting phrase specifying pins CA0 to CA5 (63 phrases). The start address, stop address, sampling frequency, and ADPCM bit length which specify the playback area for each phrase are written in the index area of the serial voice ROM. When the playback operation is started, the MSM6688 fetches these data from the index area. 39/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Deleting phrases 1. Deleting all phrases All 63 phrases ch01 through ch3F can be deleted by specifying ch00 and applying a low pulse to the DEL pin. When all phrases are deleted, all phrases ch01-ch3F (63 phrases) go to the unrecorded status and, at the same time, the initial data for address control is written in the serial registers. Therefore, whenever the MSM6688 is powered up, delete all phrases after applying a high level to the RESET pin. 2. Deleting a specified phrase By specifying one of ch01-ch3F phrases and applying a low level to the DEL pin, the specified phrase can be deleted and put to the unrecorded state. The blocks for the deleted phrases are added to available unused blocks (available recording time). 40/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Recording Method Whenever the MSM6688 is powered up, be sure to delete all phrases after applying a high level to the RESET pin. Then, start the recording operation. (1) Set recording conditions at the relevant pins. ROM pin: REC/PLAY pin: VOS pin: SAM1 and SAM2 pins: 4B /3B pin: CA0- CA5 pins: Low level High level Selection of voice triggered starting (high level enables voice activation and low level disables voice activation.) Select the sampling frequency. Select the ADPCM bit length. Specify one of 63 phrases ch01-ch3F. (2) To start recording, apply a low pulse to the ST pin. To stop recording in progress, apply a low pulse to the SP pin. When recording continues to the end of the memory capacity, recording is automatically stopped. In case of re-recording, voice data will be written in the memory block used by the specified phrase and unused memory blocks. Therefore, the voice data is overwritten on the previously recorded contents. The MON pin outputs a high level during recording. Start pulse Invalid ST (I) Stop pulse Recording in progress (stopped in the middle) (I) SP MON (O) Available memory capacity Start pulse (I) ST MON (O) Recording in progress Available memory capacity Recording is stopped automatically. 41/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Playback Method (1) Set playback conditions at the relevant pins. ROM pin: REC/PLAY pin: SAM1 and SAM2 pins: 4B/3B pin: CA0-CA5 pins: Low level Low level Select the sampling frequency. Specify the ADPCM bit length selected for recording. Specify one of 63 phases ch01-ch3F. (2) To start playback, apply a low pulse to the ST pin. When playback for the duration of the recorded data is finished, the playback is stopped automatically. To stop playback in progress, apply a low pulse to the SP pin. The MON pin outputs a high level during playback. Start pulse ST (I) Playback in progress (same as the recorded time) Playback is stopped automatically Start pulse ST SP (I) (I) Playback in progress (stopped in the middle) Recorded time Stop pulse MON (O) MON (O) By maintaining the ST pin at a low level, repeated playback is possible. ST SP (I) (I) (Stop pulse) MON (O) 1st playback 2nd playback 3rd playback 42/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ROM Playback Method (1) Apply a high level to the ROM pin. (2) Specify one of 63 phrases ch01-ch3F by setting the CA0-CA5 pins. (3) To start playback, apply a low pulse to the ST pin. To stop playback in progress, apply a low pulse to the SP pin. 43/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Voice Triggered Starting This MSM6688 has the voice triggered starting function that starts recording when the level of voice input exceeds a preset amplitude. Using the voice activated function, the unvoiced part prior to voice detection will not be recorded, so that the memory capacity can be utilized efficiently. The unvoiced parts in the middle of recording are not eliminated. In the voice triggered starting mode, recording is started when a voice input exceeds the preset thresholds. Therefore, a consonant part with a low level may not be recorded. Voice input level (ADIN pin) 1/2VDD Upper threshold +Vvds –Vvds Lower threshold Identified as voice Start signal input VDS pin L H Voice triggered starting conditions Voice triggered starting disabled Voice triggered starting disabled Voice detection threshold Vvds = VDD/32 (±160 mV) The value in parentheses is for VDD = 5.12 V. 44/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L When a low level is applied to the ST pin, the MSM6688 goes to the standby state for voice. When detecting a voiced input, it starts recording and the MON pin outputs a high level. Start pulse ST SP (I) (I) Stop pulse MON (O) Recording in progress Standby for voice Determined as voice When a low level is applied to the SP pin during standby state for voice, the MSM6688 finishes the standby state for voice and goes to the standby state for recording. Start pulse ST SP (I ) (I) Standby for recording Standby for voice Stop pulse Standby for recording 45/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Method of Temporarily Stopping Record/Playback by Pause Function By applying a low pulse to the PAUSE pin during record/playback, record/playback operation can be stopped temporarily. To resume record/playback, apply a low pulse to the ST pin. To stop record/playback, apply a low pulse to the SP pin. Start pulse ST (I) Pause pulse Pause Start pulse PAUSE (I) Resume Start pulse ST SP (I) (I) Pause pulse Pause Stop pulse PAUSE (I) Record/Playback finished When record/playback is resumed after temporary stop, the voice triggered starting circuit is not operated and recording is started when a start low pulse is applied to SP pin. 46/167 DVDD DVDD’ AVDD VCC SAD REC/PLAY SADX DEL SADX OKI Semiconductor ST SAS SADY SAS SADY SAS SAS SASX SASY TAS VCC SADX SADX MSM6685A MSM6685A MSM6685A SP TAS TAS RWCK RWC WE WE TAS RWCK RDCK DI/O DIN DOUT DROM SADY APPLICATION CIRCUIT MSM6596A-XXX PAUSE PDWN TEST TEST CS1CS2 VSS DOUT TEST RESET TAS RWCK WE DI/O 8M SERIAL REGISTER MSM6685A 2M SERIAL VOICE ROM MSM6596A-XXX RSEL1 RSEL2 SAM1 SAM2 TEST NC CS VSS DROM PDMD MCUM VDS 4B/3B CS1 CS2 SW Phrase selector CS3 CS4 CA0 CA1 CA2 CA3 CA4 CA5 MIN MOUT ROM Circuit Diagram 1: Application circuit in standalone mode with 8M bit serial registers and 2M bit serial voice ROMs ADPCM SOLID-STATE RECORDER IC MSM6688 4.096 MHz Speaker drive amplifier XT LIN XT MON NAR LOUT AMON FIN FOUT ADIN AOUT FEDL6688-6688L-04 MSM6688/6688L The circuit diagram 1 shows an application circuit example where the MSM6688 is used in the stand-alone mode and four 8M bit serial registers and two 2M bit serial voice ROMs also connected. DGND AGND SGC SG + + 47/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L (2) MICROCONTROLLER INTERFACE MODE (FOR MSM6688 (5 V VERSION) AND MSM6688L (3 V VERSION)) FEATURES • • • • • • 3-bit or 4-bit ADPCM Built-in 12-bit AD converter Built-in12-bit DA converter Built-in microphone amplifier Built-in low-pass filter Attenuation characteristics –40 dB/oct External only registers (for variable messages) MSM6688 (5 V version) - Serial registers, 32M bits maximum One 4M bit serial register (MSM6684B) can be driven directly Up to four 8M bit serial register (MSM6685A) can be driven directly MSM6688L (3 V version) - Serial registers, 4M bits maximum One 4M bit serial register (MSM66V84B) can be driven directly External only ROMs (for fixed messages) - Serial voice ROMs, 4M bits maximum 1M bit serial voice ROM (MSM6595A) can be driven directly 2M bit serial voice ROM (MSM6596A) can be driven directly 3M bit serial voice ROM (MSM6597A) can be driven directly Sampling frequency 4.0 kHz, 5.3 kHz, 6.4 kHz or 8.0 kHz (master clock frequency = 4.096 MHz) 8.0 kHz, 10.6 kHz, 12.8 kHz or 16.0 kHz (master clock frequency = 8.192 MHz) Number of phrases 63 phrases for variable messages 63 phrases for fixed messages Maximum recording time (when external 32M bit RAM is connected) 34 minutes (for 16K bps ADPCM) 23 minutes (for 24K bps ADPCM) 17 minutes (for 32K bps ADPCM) Voice triggered starting function Pause function Master clock frequency: 4.096 to 8.192 MHz Power supply voltage MSM6688: Single 5 V power supply MSM6688L: Single 3 V power supply Package options: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (MSM6688GS-2K) 56-pin plastic QFP (QFP56-P-910-0.65-2K) (MSM6688LGS-2K) 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) (MSM6688LTS-K) • • • • • • • • • 48/167 OKI Semiconductor BLOCK DIAGRAM NAR VPM RPM BUSY D3 D2 D1 D0 WR RD CE CE TEST TEST Status Register MCU I/F Test Circuit I/O Data DI/O DROM SADX SADY TAS RWCK Register MCUM RESET Controller Address Controller PDWN ACON Timing Controller MON ADPCM Analyzer/Synthesizer WE CS1 CS2 CS3 CS4 XT XT OSC RSEL1 RSEL2 DVDD MIN LPF 12-bit ADC – + 12-bit DAC SG Circuit MOUT DVDD’ AVDD DGND AGND LIN – + FEDL6688-6688L-04 MSM6688/6688L LOUT AMON FIN AOUT FOUT ADIN SG SGC 49/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L PIN CONFIGURATION (TOP VIEW) CE RD WR RESET NAR MON RWCK DVDD XT XT WE DROM DI/0 CS4 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D0 D1 D2 D3 BUSY RPM VPM ACON TEST MCUM CE TEST TEST TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CS3 CS2 CS1 SADX SADY TAS SAS PDWN TEST TEST RSEL2 RSEL1 DGND AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CE RD WR RESET NAR MON NC RWCK DVDD XT XT NC WE DROM DI/0 CS4 TEST ADIN FOUT AOUT AMON FIN DVDD’ AVDD SG SGC LOUT LIN MOUT MIN 56-Pin Plastic QFP D0 D1 D2 D3 NC BUSY RPM VPM ACON TEST MCUM NC CE TEST TEST TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CS3 NC CS2 CS1 SADX SADY TAS SAS PDWN NC TEST TEST RSEL2 RSEL1 DGND AGND TEST NC ADIN NC FOUT AOUT FIN AMON AVDD SG SGC LOUT LIN MOUT MIN NC NC: No connection 64-Pin Plastic TQFP 50/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L PIN DESCRIPTIONS QFP 49 21 22 30 29 23 24 28 26 27 25 20 19 17 16 18 39 38 Pin TQFP 56 — 25 34 33 26 27 31 29 30 28 24 23 21 19 22 44 43 Symbol DVDD DVDD’ AVDD DGND AGND SG SGC MIN LIN MOUT LOUT AMON FIN FOUT ADIN AOUT SADX SADY Type — — — — — O I O O I O I O Description Digital power supply pin. Insert a bypass capacitor of 0.1 µF or more between this pin and the DGND pin. Digital power supply pin Analog power supply pin. Insert a bypass capacitor of 0.1 µF or more between this pin and the AGND pin. Digital ground pin Analog ground pin Output pin for analog circuit reference voltage (signal ground) Inverting input pin of the built-in OP amplifier. Non-inverting input pin is internally connected to SG (signal ground). MOUT and LOUT are output pins of the built-in OP amplifier for MIN and LIN, respectively. This pin is connected to the LOUT pin in the recording mode and to the DA converter output in the playback mode. Used to connect the built-in LPF input (FIN pin). Input pin of built-in LPF Output pin of built-in LPF. Used to connect the AD converter input (ADIN pin). Input pin of the built-in 12-bit AD converter Output pin of the built-in LPF. This pin outputs playback waveforms and used to connect an external speaker drive amplifier. (Serial Address Data) SADX is used to connect the SAD pin of each external serial register and the SADX pin of each external serial voice ROM. SADY is used to connect the SADY pin of each external serial voice ROM. Outputs of starting address of read/write. (Serial Address Strobe) Used to connect the SAS pin of external serial register and the SASX and SASY pins of external serial voice ROM Clock pin to write the serial address. (Transfer Address Strobe) Used to connect the TAS pin of each external serial register and serial voice ROM. This pin outputs address strobe outputs to set the serial address data from the SADX and SADY pins into the internal address counter of each serial register and serial voice ROM. (Read/Write Clock) Used to connect the RWCK pin of each external serial register and the RDCK pin of each external serial voice ROM. This pin outputs a clock to read data from or write it into each external serial register. (Write Enable) Used to connect the WE pin of each external serial register. This pin outputs WE signal to select either read or write mode. (Data I/O) Used to connect the DIN and DOUT pins of DRAM and serial register. This pin outputs the data to be written into the serial register or inputs the data read from the serial registers. (Data ROM) Used to connect the DOUT pin of each external serial voice ROM. O 36 41 SAS O 37 42 TAS O 50 57 RWCK O 46 52 WE O 44 45 50 51 DI/O DROM I/O I 51/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L QFP 40 41 42 43 Pin TQFP 45 46 48 49 Symbol CS1 CS2 CS3 CS4 Type Description (Chip Select) Used to connect the CS pin of serial register and the CS (CS1, CS2, CS3) pins of each serial voice ROM. (Register Select) These are used to select the number of external serial registers. O 31 32 35 36 RSEL1 RSEL2 I RSEL2 RSEL1 Number of serial registers L L 1 L H 2 H L 3 H H 4 10 11 MCUM I 53 61 RESET I 35 40 PDWN I This pin is used to select either the stand-alone mode or the microcontroller interface mode. Low level: Stand-alone mode High level: Microcontroller interface mode A high input level at this pin causes the MSM6688/6688L to be initialized and to go into the power down state. (Power Down) When a low level is input to this pin, the MSM6688 goes to the power down state. Unlike the RESET pin, this pin does not force to reset the MSM6688/6688L. When an low level is applied to this PDWN pin during recording operation, the MSM6688/6688L is halted, and will be maintained in the power down state while PDWN is low. After this pin is restored to a high level, postprocessing for recording will be performed. Bi-directional data bus to transfer commands and data to and from an external microcontroller. Write pulse input pin. Inputting a low pulse to this WR pin causes a command or data to be input via D0-D3 pins. Read pulse input pin. Inputting a low pulse to this RD pin causes status bits or data to be output via D0-D3 pins. Chip enable input pins. When the CE pin is set to a low level or the CE pin is set to a high level, the write pulse (WR), read pulse (RD) can be accepted. When the CE pin is set to a high level or CE pin is set to a low level, the write pulse (WR) and read pulse (RD) cannot be accepted so that data cannot be transferred to and from via D0-D3 pins. Outputs a high level while a command is being executed. When this pin is held high, do not apply any data to D0-D3 pins. The state of this BUSY pin is the same as the contents of the BUSY bit of the status register. Outputs a high level during recording or playback operation. The state of this RPM is the same as the contents of the RPM bit of the status register. Outputs a high level during the standby for voice after the start of voice triggered recording and the record/playback is stopped temporarily by inputting the PAUSE command. The state of this VPM pin is the same as the contents of the VPM bit of the status register. 1 2 3 4 54 55 1 2 3 4 62 63 D0 D1 D2 D3 WR RD I/O I I 56 11 64 13 CE CE I 5 6 BUSY O 6 7 RPM O 7 8 VPM O 52/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Pin QFP TQFP Symbol Type Description This NAR bit indicates whether the phrase designation by the CHAN command is enabled or disabled. In the ROM playback operation, specify the next phrase after making sure that the NAR output is high, and input the START command. Used to select the use or nonuse of the pop noise suppression circuit at the analog output (AOUT) pin. When low level, the pop noise suppression circuit is not used. When high level, the pop noise suppression circuit is used. Used to connect an oscillator. When an external clock is used, input the clock through this pin. At the power down state, this pin must be set to the ground level. Used to connect an oscillator, when an external clock is used, this pin must be left open. Outputs a high level while the record/playback operation is being performed. Outputs a synchronizing clock while record/playback activated by the EXT command is being performed. Used to test the MSM6688/6688L. Input a low level to the TEST pin and a high level to the TEST pin. 52 60 NAR O 8 9 ACON I 47 48 51 54 55 59 XT XT MON TEST TEST I O O I 12-15, 34 14-17, 38 9, 33 10, 37 53/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version)) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG Condition Ta = 25°C Ta = 25°C — Rating –0.3 to +7.0 –0.3 to VDD+0.3 –55 to +150 Unit V V °C RECOMMENDED OPERATING CONDITIONS (for R MSM6688 (5 V Version)) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition DGND = AGND = 0 V — — Range 3.5 to 5.5 (Note 3) –40 to +85 4.0 to 8.192 Unit V °C MHz ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version)) DC Characteristics DVDD = DVDD’ = AVDD = 4.5 to 5.5 V (Note 3) DGND = AGND = 0 V, Ta = –40 to +85°C Parameter High input voltage Low input voltage High output voltage Low output voltage High input current (Note 1) High input current (Note 2) Low input current (Note 1) Low input current (Note 2) Operating current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD Condition — — IOH = –40 µA IOL = 2 mA VIH = VDD VIH = VDD VIL = GND VIL = GND fOSC = 8 MHz, no load During power down, no load Standby current Consumption IDDS Ta = –40 to +70°C During power down, no load Ta = –40 to +85°C — — 50 µA Min. 0.8 × VDD — VDD – 0.3 — — — –10 –20 — Typ. — — — — — — — — 15 Max. — 0.2 × VDD — 0.45 10 20 — — 30 Unit V V V V µA µA µA µA mA — — 10 µA Notes: 1. Applies to all input pins excluding the XT pin. 2. Applies to the XT pin. 3. Recording and playback should be performed at a power supply voltage of 4.5 to 5.5 V. For other operations such as backup for a serial register, the IC operates at 3.5 to 5.5 V. 54/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Analog Characteristics DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C Parameter DA output relative error FIN admissible input voltage range FIN input impedance ADIN admissible input voltage range ADIN input impedance Op-amp open loop gain Op-amp input impedance Op-amp load resistance AOUT load resistance FOUT load resistance Symbol |VDAE| VFIN RFIN VADIN RADIN GOP RINA ROUTA RAOUT RFOUT Condition No load — — — — fIN = 0 to 4 kHz — — — — Min. — 1 1 0 1 40 1 200 50 50 Typ. — — — — — — — — — — Max. — VDD – 1 — VDD — — — — — — Unit mV V MΩ V MΩ dB MΩ kΩ kΩ kΩ 55/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L AC Characteristics DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter RESET pulse width RESET execution time PDWN low level time PDWN high level time Oscillating time after input of PDWN BUSY time after release of PDWN RD pulse width Setup and hold time of CE and CE for RD Time from RD fall to data valid Time from RD rise to data float WR pulse width Setup and hold time of CE and CE for WR Data setup time to WR rise Data hold time from WR rise RD and WR disable time BUSY time after release of RESET (Note 1) * ** ** ** ** * BUSY time after input of 1-nibble command BUSY time after input of 2-nibble command BUSY time after input of 3-nibble command BUSY time after input of 2-nibble or 3-nibble command data WAIT time after input of BLKRD command (Note 1) * * * * (Note 1) * Symbol tRST tREX tPDL tPDH tPX tBPD tRR tCR tDRE tDRF tWW tCW tDWS tDWH tDRW tBR tB1 tB2 tB3 tBD tWBR tWDR tBAW tBAD tWAR tWDR tAD1 Min. 1 — 500 500 125 0.25 200 30 — — 200 30 100 30 250 — — — — — 270 50 — — 270 50 — Typ. — 1 — — — — — — — 10 — — — — — — — — — — — — — — — — 1 Max. — — — — 500 80 — — 200 50 — — — — — 1 16 16 16 16 — — 270 50 — — — Unit µs ms µs µs µs ms ns ns ns ns ns ns ns ns ns ms µs µs µs µs µs µs µs µs µs µs ms WAIT time after output of BLKRD command block data * BUSY time after input of ADRWR command BUSY time after input of ADRWR command address data WAIT time after input of ADRRD command WAIT time after output of ADRRD command address data Address control time at start of record/playback * * * * * Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. Note: 1. The oscillation startup stabilization time is added to tREX, tBPD and tBR. The oscillation startup stabilization time is several tens of milliseconds for crystal oscillators and is several hundreds of microseconds for ceramic oscillators. 56/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter Time from input of START command to MON rise Flex record Flex playback ROM playback Flex record Time from input of STOP command to MON fall Flex playback ROM playback Time from input of START command to setting of RPM bit Time from input of STOP command to end of record/playback Time from input of STOP command to release of standby for voice Flex record Direct record * * * * * * * * * * * * ** Symbol tSTCM tSTCM tSTCM tSTCM tSPCM tSPCM tSPCM tSPCM tSTCR tSPCR tSPCV tSPCV tSTCN tMID tPSCP tSTCP tSPCP tWCRW tWRC tWWD tWPL tWSP tWRW tWA1 tWA2 tWRC tWWD tWPL tWSP Min. — — — — — — — — — — — — — — — — — 770 16 50 50 50 16 16 270 16 50 50 16 Typ. — — — — — — — — — — — — — 1.25 — — — — — — — — — — — — — — — Max. 50 20 1 1 80 2 2 2 16 2 80 2 16 — 16 500 500 — — — — — — — — — — — — Unit ms ms ms ms ms ms ms ms µs ms ms ms µs ms µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs Direct record/playback * Direct record/playback * Time from input of START command to NAR bit fall during continuos playback Unvoiced time between phrases during continuous playback Time from input of PAUSE command to setting of VPM bit Time from input of START command during pause to resetting of VPM bit ** Time from input of STOP command during pause to resetting of VPM bit WAIT time after input of command CHRW command WAIT time after input of write data WAIT time after input of STOP command WAIT time after input of command WAIT time after input of address (2nd-5th nibbles) ** * * * * * WAIT time after input of REC command * WAIT time after input of PLAY command * DTRW and WAIT time after input of address (6th nibble) * DTRD commands WAIT time after input of REC command * WAIT time after input of write data * WAIT time after input of PLAY command * WAIT time after input of STOP command * Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. 57/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L DVDD = DVDD’ = AVDD = 4.5 to 5.5 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter WAIT time for deletion of all phrases after input of DEL command * WAIT time for deletion of a specified phase after input of DEL command Time to start of DC level transition after input of LEV command DC level transition time (GND to 1/2 VDD) DC level transition time (1/2 VDD to GND) Time from input of EXT command to MON rise MON high level time MON low level time Time from MON rise to RD pulse rise during recording * * * * ** ** ** ** Symbol tWBLA tWBLI tLV tAOR tAOF tEM tMH tML tERD tEWR tWE1 tESP tWEX Min. 550 70 — — — — — — — — 16 — — Typ. — — — 64 256 — 31 94 — — — — — Max. — — 16 — — 330 — — 120 120 — 100 250 Unit ms ms µs ms ms µs µs µs µs µs µs µs µs Time from MON rise to WR pulse rise EXT during playback ** command Time from ADPCM data WR pulse to input of STOP command during playback ** Time from MON rise to input of STOP command Time from input of STOP command to end of record/playback ** ** Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. 58/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ABSOLUTE MAXIMUM RATINGS (for MSM6688L (3 V Version)) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG Condition Ta = 25°C Ta = 25°C — Rating –0.3 to +7.0 –0.3 to VDD+0.3 –55 to +150 Unit V V °C RECOMMENDED OPERATING CONDITIONS (for MSM6688L (3 V Version)) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition DGND = AGND = 0 V — — Range 2.7 to 3.6 –40 to +85 4.0 to 8.192 Unit V °C MHz ELECTRICAL CHARACTERISTICS (for MSM6688L (3 V Version)) DC Characteristics DVDD = DVDD’ = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = –40 to +85°C Parameter High input voltage Low input voltage High output voltage Low output voltage High input current (Note 1) High input current (Note 2) Low input current (Note 1) Low input current (Note 2) Operating current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD Condition — — IOH = –40 µA IOL = 2 mA VIH = VDD VIH = VDD VIL = GND VIL = GND fOSC = 8 MHz, no load During power down, no load Standby current Consumption IDDS Ta = –40 to +70°C During power down, no load Ta = –40 to +85°C — — 100 µA Min. 0.85 × VDD — VDD – 0.3 — — — –10 –20 — Typ. — — — — — — — — 15 Max. — 0.15 × VDD — 0.45 10 20 — — 30 Unit V V V V µA µA µA µA mA µA — — 15 Notes: 1. Applies to all input pins excluding the XT pin. 2. Applies to the XT pin. 59/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Analog Characteristics DVDD = DVDD’ = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = –40 to +85°C Parameter DA output relative error FIN admissible input voltage range FIN input impedance ADIN admissible input voltage range ADIN input impedance Op-amp open loop gain Op-amp input impedance Op-amp load resistance AOUT load resistance FOUT load resistance Symbol |VDAE| VFIN RFIN VADIN RADIN GOP RINA ROUTA RAOUT RFOUT Condition No load — — — — fIN = 0 to 4 kHz — — — — Min. — 1/4 × VDD 1 0 1 40 1 200 50 50 Typ. — — — — — — — — — — Max. 10 3/4 × VDD — VDD — — — — — — Unit mV V MΩ V MΩ dB MΩ kΩ kΩ kΩ 60/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L AC Characteristics DVDD = DVDD’ = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter RESET pulse width RESET execution time PDWN low level time PDWN high level time Oscillating time after input of PDWN BUSY time after release of PDWN RD pulse width Setup and hold time of CE and CE for RD Time from RD fall to data valid Time from RD rise to data float WR pulse width Setup and hold time of CE and CE for WR Data setup time to WR rise Data hold time from WR rise RD and WR disable time BUSY time after release of RESET (Note 1) * ** ** ** ** * BUSY time after input of 1-nibble command BUSY time after input of 2-nibble command BUSY time after input of 3-nibble command BUSY time after input of 2-nibble or 3-nibble command data WAIT time after input of BLKRD command (Note 1) * * * * (Note 1) * Symbol tRST tREX tPDL tPDH tPX tBPD tRR tCR tDRE tDRF tWW tCW tDWS tDWH tDRW tBR tB1 tB2 tB3 tBD tWBR tWDR tBAW tBAD tWAR tWDR tAD1 Min. 1 — 500 500 125 0.25 200 30 — — 200 30 100 30 250 — — — — — 270 50 — — 270 50 — Typ. — 1 — — — — — — — 10 — — — — — — — — — — — — — — — — 1 Max. — — — — 500 80 — — 200 50 — — — — — 1 16 16 16 16 — — 270 50 — — — Unit µs ms µs µs µs ms ns ns ns ns ns ns ns ns ns ms µs µs µs µs µs µs µs µs µs µs ms WAIT time after output of BLKRD command block data * BUSY time after input of ADRWR command BUSY time after input of ADRWR command address data WAIT time after input of ADRRD command WAIT time after output of ADRRD command address data Address control time at start of record/playback * * * * * Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. Note: 1. The oscillation startup stabilization time is added to tREX, tBPD and tBR. The oscillation startup stabilization time is several tens of milliseconds for crystal oscillators and is several hundreds of microseconds for ceramic oscillators. 61/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L DVDD = DVDD’ = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter Flex record Time from input of START command to MON rise Flex playback ROM playback Flex record Time from input of STOP command to MON fall Flex playback ROM playback * * * * * * Symbol tSTCM tSTCM tSTCM tSTCM tSPCM tSPCM tSPCM tSPCM tSTCR tSPCR tSPCV tSPCV tSTCN tMID tPSCP tSTCP tSPCP tWCRW tWRC tWWD tWPL tWSP tWRW tWA1 tWA2 tWRC tWWD tWPL tWSP Min. — — — — — — — — — — — — — — — — — 770 16 50 50 50 16 16 270 16 50 50 16 Typ. — — — — — — — — — — — — — 1.25 — — — — — — — — — — — — — — — Max. 50 20 1 1 80 2 2 2 16 2 80 2 16 — 16 500 500 — — — — — — — — — — — — Unit ms ms ms ms ms ms ms ms µs ms ms ms µs ms µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs Direct record/playback * Direct record/playback * Time from input of START command to setting of RPM bit * Time from input of STOP command to end of record/playback * Flex record * Time from input of STOP command to release of Direct record * standby for voice Time from input of START command to NAR bit fall during continuos playback * Unvoiced time between phrases during continuous playback * Time from input of PAUSE command to setting of VPM bit ** Time from input of START command during pause to resetting of VPM bit ** Time from input of STOP command during pause to resetting of VPM bit ** WAIT time after input of command * WAIT time after input of REC command * WAIT time after input of write data * WAIT time after input of PLAY command * WAIT time after input of STOP command * WAIT time after input of command * WAIT time after input of address (2nd-5th nibbles) * WAIT time after input of address DTRW * and DTRD (6th nibble) commands WAIT time after input of REC command * WAIT time after input of write data * WAIT time after input of PLAY command * WAIT time after input of STOP command * CHRW command Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. 62/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L DVDD = DVDD’ = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = –40 to +85°C fOSC = 4.096 MHz, fSAMP = 8.0 kHz Parameter WAIT time for deletion of all phrases after input of DEL command * WAIT time for deletion of a specified phrase after input of DEL command * Symbol tWBLA tWBLI tLV tAOR tAOF tEM tMH tML tERD tEWR tWE1 tESP tWEX Min. 550 70 — — — — — — — — 16 — — Typ. — — — 64 256 — 31 94 — — — — — Max. — — 16 — — 330 — — 120 120 — 100 250 Unit ms ms µs ms ms µs µs µs µs µs µs µs µs Time to start of DC level transition after input of LEV command * DC level transition time (GND to 1/2 VDD) DC level transition time (1/2 VDD to GND) Time from input of EXT command to MON rise MON high level time MON low level time Time from MON rise to RD pulse rise during recording * * ** ** ** ** Time from MON rise to WR pulse rise EXT during playback ** command Time from ADPCM data WR pulse to input of STOP command during playback ** Time from MON rise to input of STOP command ** Time from input of STOP command to end of record/playback ** Items with * are proportional to the period of master clock frequency fOSC. Items with ** are proportional to the period of the master clock frequency fOSC, and are also proportional to the sampling frequency fSAMP during record/playback. 63/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L TIMING DIAGRAMS Reset Function VDD tRST RESET (I) tREX Hi-Z BUSY (O) Undefined Power down Standby for Reset operation record/playback in progress 64/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Power Down by the PDWN pin tPDL PDWN (I) tPDH tPX Note 1 XT XT (I) (O) Oscillation in progress Oscillation in progress tBPD BUSY (O) RPM VPM NAR (O) (O) (O) Hi-Z Hi-Z Hi-Z Hi-Z Power down Postprocessing Standby WR and RD pulses are not accepted Note: 1. When an external clock is used, apply a low level to the PDWN pin and then continue to apply the external clock to the XT pin for tPX. 65/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Data Read Timing (RD Pulse) CE CE (I) (I) tCR RD (I) tRR tDRE D0-D3 (I/O) tDRF tCR Data Write Timing (WR Pulse) CE CE (I) (I) tCW WR (I) tWW tDWS D0-D3 (I/O) tDWH tCW 66/167 OKI Semiconductor Inputting 1-Nibble Commands (NOP, PAUSE, PLAY, REC, START, STOP and DEL Commands) WR tDRW (I) RD Status output Status output (I) D0-D3 tB1, tWBLA, tWBL1 Command input (I/O) Status register BUSY bit tB1: tWBLA: tWBL1: NOP, PAUSE, PLAY, REC, START, and STOP commands DEL command (deletion of all phrases) DEL command (deletion of a specified phrase) FEDL6688-6688L-04 MSM6688/6688L 67/167 OKI Semiconductor Inputting 2-Nibble Commands (SAMP, VDS, and LEV Commands) WR tDRW (I) RD Status output (I) D0-D3 Command input (1st nibble) Data input (2nd nibble) tBD tB2 (I/O) Status register BUSY bit The LEV command is used to specify the playback level. See the timing diagram for DC level transition by the LEV command. FEDL6688-6688L-04 MSM6688/6688L 68/167 OKI Semiconductor Inputting 3-Nibble Commands (CHAN and BLKWR Commands) WR tDRW (I) RD Status output (I) D0-D3 Command input (1st nibble) tB3 Data input (2nd nibble) tBD (I/O) Data input (3rd nibble) tBD Status register BUSY bit FEDL6688-6688L-04 MSM6688/6688L 69/167 OKI Semiconductor Inputting the BLKRD Command WR tWBR tWDR tWDR (I) Input of WR and RD pulses enabled RD (I) D0-D3 Status output Command input (1st nibble) Data output (2nd nibble) (I/O) Data output (3rd nibble) Status register BUSY bit 1. After making sure that the MSM6688/6688L is not in the busy state by checking the BUSY bit of the status register, input the BLKRD command. 2. Then, the data is read according to the 2nd and 3rd nibble command. However, the status of the BUSY bit cannot be verified by inputting the RD pulse. Therefore, input the RD pulse either after the waiting time tWBR or tWDR or after verifying the BUSY state at BUSY output pin. FEDL6688-6688L-04 MSM6688/6688L 70/167 OKI Semiconductor Inputting the ADRWR Command WR (I) RD (I) D0-D3 Status output ADRWR command Address data input (1st nibble) input (2nd nibble) tBAW tBAD Address data input (3rd nibble) tBAD (I/O) Address data input (11th nibble) Input of WR tBAD pulse enabled Status register BUSY bit 1. After making sure that the MSM6688/6688L is not in the busy state by checking the BUSY bit of the status register, input the ADRWR command. 2. Then, input 2nd-11th nibble address data after making sure that the MSM6688 is not in the BUSY state by one of the following two methods. • Check of the BUSY bit in the status register FEDL6688-6688L-04 • Input the next WR pulse after the waiting time tBAW or tBAD. MSM6688/6688L 71/167 OKI Semiconductor Inputting the ADRRD Command WR tWAR tWDR tWDR Input of WR and RD pulses enabled (I) RD (I) D0-D3 Command input (1st nibble) Address data Address data output output (2nd nibble) (3rd nibble) Address data output (11th nibble) (I/O) Status output Status register BUSY bit 1. After making sure that the MSM6688/6688L is not in the busy state by checking the BUSY bit of the status register, input the ADRRD command. 2. Then, the address data is read according to 2nd through 11th nibble command. The state of the BUSY bit cannot be checked by the RD pulse. Therefore, input the RD pulse either after the waiting time tWAR or tWDR or after verifying the BUSY state at the BUSY output pin. FEDL6688-6688L-04 MSM6688/6688L 72/167 Timing for Record/Playback by START Command OKI Semiconductor RESET (I) WR (I) D0-D3 START command tSTCM (Note) (STOP tSPCM (Note) (I/O) MON tB1 tB1 (I) Status register tBR BUSY bit RPM bit NAR bit tSTCR tAD1 tSPCR AOUT (playback) Standby Address control (O) Power down Record/playback Standby Address control Power down FEDL6688-6688L-04 MSM6688/6688L Note: tSTCM and tSPCM vary depending on the control mode for record/playback and on record or playback mode. 73/167 Timing for Voice Triggered Recording OKI Semiconductor WR (I) D0-D3 START command tSPCV (Note) (STOP command) (STOP command) tSPCM (I/O) MON (O) Status register tB1 tB1 tB1 BUSY bit RPM bit VPM bit NAR bit tSTCR tAD1 tSPCR Standby Standby for voice Address control Voice detected Recording Standby Address control If the STOP command is input during standby for voice, this state is changed to the standby for recording. FEDL6688-6688L-04 MSM6688/6688L Note: tspcv varies depending on the recording mode (flex recording or direct recording). 74/167 OKI Semiconductor Timing for Continuous ROM Playback by Input of Address Code WR (I) D0-D3 tSTCM START d CHAN command (2nd phrase) START command (I/O) CHAN command (1st phrase) MON tSTCN (O) Status register tSTCR RPM bit NAR bit tAD1 tMID AOUT (O) Standby Address control 1st phrase playback Address control 2nd phrase playback Standby FEDL6688-6688L-04 MSM6688/6688L 75/167 OKI Semiconductor Timing for Record/Playback Pause Operation by PAUSE Command WR (I) RD (I) D0-D3 START tSTCM command START command PAUSE command tSPCM tB1 tB1 tB1 tB1 tB1 PAUSE command (I/O) STOP command MON (O) Status register BUSY bit tSPCP tPSCP RPM bit tSTCR tPSCP tSTCP VPM bit Standby Record/playback Pause Record/playback Pause Standby FEDL6688-6688L-04 MSM6688/6688L 76/167 OKI Semiconductor Timing for Data Transfer by CHRW Command tWCRW tWRC tWWD tWSP Next command input enabled WR tWPL (I) RD (I) D0-D3 REC command Write data Read data PLAY command (I/O) STOP command Command execution Write access Read access FEDL6688-6688L-04 MSM6688/6688L 77/167 OKI Semiconductor Timing for Data Transfer by DTRW Command tWRW tWA1 tWA1 tWA1 tWA1 tWA2 tWWD tWRC tWSP Next command input enabled WR tWPL (I) RD (I) D0-D3 (I/O) REC Write data command PLAY Read data command STOP command DTRW command X12 to X15 Dummy X4 to X7 “0h” X0 to X3 X8 to X11 Address input Write access Read access FEDL6688-6688L-04 MSM6688/6688L 78/167 Timing for Data Read by DTRD command OKI Semiconductor tWRW tWA1 tWA1 tWA1 tWA1 command enabled tWA2 tWSP Input of next WR tWPL (I) RD (I) D0-D3 (I/O) PLAY Read data command STOP command DTRD Dummy “0h” Y address X4 to X7 command X0 to X3 X8 to X11 Address input Read access FEDL6688-6688L-04 MSM6688/6688L 79/167 OKI Semiconductor Recording by EXT Command RESET (I) WR (I) RD (I) D0-D3 EXT command ADPCM data ADPCM data tERD tESP tWEX tMH tML tEM (I/O) STOP command Next command input enable REC command MON (O) Standby Recording Standby Power down Power down Notes: 1. When reading the ADPCM data, input the RD pulse to satisfy time tERD from rise of MON to rise of the rise of RD pulse. 2. Input the STOP command when the MON pin is “H”, after reading the ADPCM data. At that time, it is required to satisfy time tESP from rise of MON to input of the STOP command. FEDL6688-6688L-04 MSM6688/6688L 80/167 Playback by EXT Command RESET tWE1 OKI Semiconductor (I) WR (I) RD (I) D0-D3 ADPCM data tMH tML tEWR tESP tWEX ADPCM data (I/O) STOP command Next command input enable MON (O) EXT PLAY command command tEM Status output AOUT (O) 1/2 VDD level 1/2 VDD level GND level Playback Standby Power down GND level Standby Power down Notes: 1. When writing the ADPCM data, input the WR pulse to satisfy time tEWR from rise of MON to rise of the WR pulse. 2. Input the STOP command when the MON pin is “H”, after writing the ADPCM data. At that time, it is required to satisfy time tESP from rise of MON to input of the STOP command, and interval tWE1 between the WR pulse and the STOP command pulse. 3. Input the ADPCM data beginning with the top of a phrase every sampling period sequentially. If the ADPCM data is input beginning with the second or following part of a phrase or with data missing, normal (playback) waveforms cannot be regenerated. FEDL6688-6688L-04 MSM6688/6688L 81/167 Timing for DC Level Transition by LEV Command OKI Semiconductor RESET (I) WR (I) D0-D3 LEV command tLV tAOR tLV tAOF PLAY command LEV command (I/O) PLAY command Status register BUSY bit NAR bit AOUT GND level (O) 1/2 VDD level GND level Power down DC level transition Standby Record/playback DC level transition Standby Power down FEDL6688-6688L-04 MSM6688/6688L 82/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L FUNCTIONAL DESCRIPTION Recording Time and Memory Capacity The recording time depends on the memory capacity of the external serial registers, sampling frequency, and ADPCM bit length, and is given by 1.024 × memory capacity (K bits) Recording time = (seconds) sampling frequency (kHz) × bit length (bits) 4096 For example, if the sampling frequency is kHz (= 5.333 kHz), ADPCM bit length is 3 bits, and four 8M 768 bit serial registers are used, the recording time can be obtained as follows. 1.024 × (8192 × 4 – 64) = 2093 seconds 5.333 × 3 = 34 minutes 53 seconds In the above equation, the memory capacity is obtained by subtracting the memory capacity (64K bits) for the channel index area from the total memory capacity. Recording time = Connection of an Oscillator Connect a ceramic oscillator or a crystal oscillator to XT and XT pins as shown below. The optimal load capacities when connecting ceramic oscillators from MURATA MFG., KYOCERA CORPORATION, and TDK CORPORATION are shown below for reference. MSM6688 MSM6688L XT C1 XT C2 1. MSM6688 Ceramic oscillator Type CSTLS4M00G53-B0 (with capacitor) MURATA MFG. CSTCR4M00G53-R0 (with capacitor) CSTLS6M00G53-B0 (with capacitor) CSTCR6M00G53-R0 (with capacitor) CSTLS8M00G53-B0 (with capacitor) CSTCC8M00G53-R0 (with capacitor) Freq. (MHz) 4.0 Optimal load capacity C1 (pF) C2 (pF) Power supply voltage (V) Operating temperature (°C) 6.0 — — 3.5 to 5.5 –40 to +85 8.0 83/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Ceramic oscillator Type KBR-4.0MSA KBR-4.0MKS (with capacitor) KYOCERA CORP. PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS (with capacitor) PBRC6.00A PBRC6.00B KBR-8.0M PBRC8.00A PBRC8.00B 8.0 Freq. (MHz) Optimal load capacity C1 (pF) C2 (pF) Power supply voltage (V) Operating temperature (°C) 4.0 6.0 33 33 3.5 to 5.5 –40 to +85 84/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. MSM6688L Ceramic oscillator Type CSTLS4M00G53-B0 (with capacitor) MURATA MFG. CSTCR4M00G53-R0 (with capacitor) CSTLS6M00G53-B0 (with capacitor) CSTCR6M00G53-R0 (with capacitor) CSTLS8M00G53-B0 (with capacitor) CSTCC8M00G53-R0 (with capacitor) KBR-4.0MSB KBR-4.0MKC (with capacitor) PBRC4.00A KYOCERA CORP. PBRC4.00B (with capacitor) KBR-6.0MSB KBR-6.0MKC (with capacitor) PBRC6.00A PBRC6.00B (with capacitor) KBR-8.0M PBRC8.00A PBRC8.00B (with capacitor) FCR4.0M5 FCR4.0MC5 (with 30pF capacitor) TDK CORP. FCR6.0M5 FCR6.0MC5 (with 30pF capacitor) CCR6.0MC3 (with capacitor) FCR8.0M2S CCR8.0MC5 (with capacitor) 8.0 6.0 4.0 8.0 6.00 4.0 Freq. (MHz) 4.0 Optimal load capacity C1 (pF) C2 (pF) Power supply voltage (V) Operating temperature (°C) 6.0 — — 2.7 to 3.6 –40 to +85 8.0 33 33 2.7 to 3.6 –40 to +85 33 — 33 — — 33 — 33 — 33 — — 33 — 2.7 to 3.6 –40 to +85 85/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Power Supply Wiring As shown in the following diagram, supply the power to this MSM6688 from the same power source, but separate the power supply wiring to the analog portion from that to the logic position. +5 V DVDD’ DVDD AVDD MSM6688 MSM6688L DGND AGND The following connections are not permitted. Analog power supply Digital power supply DVDD DVDD’ AVDD +5 V DVDD DVDD’ AVDD Configuring SGC and SG pins The internal equivalent circuit around the SGC and SG pins is shown below. AVDD MSM6688 MSM6688L 50 kΩ (TYP) + – 50 kΩ (TYP) SGC To OP amplifier, LPF SG 20 kΩ (TYP) AGND AGND Power-down signal Switch is open at power-down AGND 86/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L The SG signal is a reference voltage (signal ground) for internal OP amplifiers and LPF. Install a capacitor between the SGC pin and AGND and between the SG pin and AGND respectively in order to make the SG signal noiseless. It is recommended to use an approx. 0.1 µF capacitor, which should be determined after evaluating the tone quality. It takes several ten msec until the DC levels such as the SG level of the analog circuit is stabilized after the power-down mode is cancelled. The larger capacitance of a capacitor connected to SGC or SG requires the longer time for stabilizing. After the power-down mode is cancelled, enter voices after the DC levels for the analog circuit has been stabilized. When the device is in power-down mode, the output voltage of the SG pin becomes unstable. Therefore, SG must not be supplied to external circuits. Otherwise, power supply current may be leaked via the internal SG circuit. Same is true for the SGC pin. Analog Input Amplifier Circuit This MSM6688 has two built-in operational amplifiers for amplifying the microphone output. Each OP amplifier is provided with the inverting input pin and output pin. The analog circuit reference voltage SG (signal ground) is connected internally to the non-inverting input of each OP amplifier. For amplification, form an inverting amplifier circuit and adjust the amplification factor by using external resistors as shown below. VIN –+ R1 MIN R2 VMO R3 MOUT – + OP amp 1 R4 LIN LOUT VLO VLO VDD VFIN (max.) 1/2VDD VFIN (min.) GND SG – + OP amp 2 VLO= R4 R3 VMO= R2 • R4 R1 • R3 VIN(V) During recording, the output VLO of OP amp 2 is connected to the input FIN of the LPF. Adjust the amplification factor by using the external resistors so that the VLO amplitude is within the FIN admissible input voltage (VFIN) range. If VLO exceeds the VFIN range, the LPF output waveform will be distorted. The table below shows an example of the allowable FIN input voltage range for the MSM6688 and MSM6688L. Parameter MSM6688 MSM6688L Power supply voltage VDD 5V 3V Allowable FIN input voltage range VFIN Min. 1V 0.75 V Max. 4V 2.25 V Allowable FIN input voltage 3 Vp-p 1.5 Vp-p The value of the OP amplifier load resistance ROUTA is 200 kΩ minimum. Therefore the values of the inverting amplifier circuit feedback resistors R2 and R4 should be 200 kΩ or more. 87/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L When OP amplifier 1 is not used and OP amplifier 2 is used, the MIN pin must be connected to AGND or AVDD, and the MOUT pin must be open. Even if amplification is unnecessary, OP amplifier 2 must be always used. Below is an example of an analog input amplifier circuit when the amplification factor is 1. Input signal AGND (or AVDD) (200 kΩ) R3 (200 kΩ) R4 MIN MOUT – + OP amplifier 1 LIN LOUT – + OP amplifier 2 MSM6688 MSM6688L SG 88/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Connection of LPF Circuit Peripherals The AMON pin is connected internally to the output of the amplifier circuit (LOUT pin) in the recording mode and to the output of the built-in DA converter in the playback mode. Therefore, connect the AMON pin directly to the input (FIN pin) of the built-in LPF. Both the FOUT and AOUT pins are the output pins of the built-in LPF. Connect the FOUT pin to the input (ADIN pin) of the built-in AD converter and connect the AOUT pin to an external speaker through an external speaker drive amplifier. In the MSM6688/6688L, the connection of each of the FOUT and AOUT pins is changed to one of the output of the LPF, GND (ground) level, and SG (signal ground) level, depending on the operation status as shown below. Analog pin FOUT pin AOUT pin At power down (RESET pin = H) GND level GND level During operation (RESET pin = L) Recording mode LPF output (recording waveform) SG level Playback mode LPF output LPF output (playback waveform) Speaker drive amplifier LIN LOUT AMON FIN AOUT FOUT ADIN – + SG DAC Record mode Playback mode Playback mode – + Power down LPF ADC Record mode SG GND – + Power down GND Note: This diagram shows the state of each switch during the recording operation. LPF Characteristics This MSM6688/6688L contains a fourth-order switched-capacitor LPF. The attenuation characteristic of this LPF is –40 dB/oct. The cut-off frequency and frequency characteristics of this LPF vary in proportion to the sampling frequency (fSAMP). The cut-off frequency is preset to 0.4 times the sampling frequency. The following graph depicts the frequency characteristics of the LPF at fSAMP = 8 kHz. [dB] 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 100 1K 10K [Hz] LPF Frequency Characteristics (fSAMP = 8.0 kHz) 89/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Full Scale of A/D and D/A Converters Parameter MSM6688 MSM6688L Full scale of A/D and D/A converters Min. (V) 0 1/4 × VDD Max. (V) VDD 3/4 × VDD Amplitude (Vp-p) VDD 1/2 × VDD 1. When the MSM6688 is used VDD (5 V) VDD–1 (4 V) 1 V (2.5 V) 2 DD 1 V (1 V) 0 V (0 V) Full scale of A/D and D/A converters LPF admissible input voltage range Note: Value in parentheses applies when VDD = 5.0 V. 2. When the MSM6688L is used VDD (3 V) 3 V (2.25 V) DD 4 1 V (1.5 V) 2 DD 1 V (0.75 V) 4 DD 0 V (0 V) Full scale of A/D and D/A converters LPF admissible input voltage range Note: Value in parentheses applies when VDD = 3.0 V. 90/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Reset Function By applying a high level to the RESET pin, the MSM6688/6688L stops oscillation to minimize current consumption and goes to the power-down state. At the same time, the control circuit is reset and initialized. When this reset operation is performed, the record/playback condition, such as sampling frequency and ADPCM bit length, and the data stored in the serial registers are set to the data stored just before the reset takes place. In this case, the playback level is set to 0 dB amplitude. If a high level is applied to the RESET pin during command execution or record/playback operation, the MSM6688/6688L is set to the power-down state and initialized state. Internal data and voice data become undefined. The following shows the power-down state of the MSM6688/6688L. (1) Oscillation is stopped and all operations of the internal circuit are halted. (2) The current consumption is minimized. When an external clock is used, apply a ground (GND) level to the XT pin at power down so that no current can flow into the oscillation circuit. (3) D0-D3 pins constituting the data bus go to the high-impedance state, independent of the state of the RD, CE, and CE pins. (4) CS1-CS4 pins are set to a high level to minimize the current consumption of external serial registers and serial voice ROMs. (5) The state of the output pins and input/output pins are as follows. Pin name SAS, TAS, CS1-CS4, RWCK SADX, WE, NAR SADY MON D0-D3, BUSY, RPM, VPM DI/O AOUT, FOUT Power down mode with RESET = “H” “H” level “H” level “L” level “L” level Hi-Z Hi-Z GND level Power down mode with PDWN = “L” “H” level “H” level or “L” level “H” level or “L” level “L” level Hi-Z “H” “L” or Hi-Z GND level After powering up the MSM6688/6688L, be sure to initialize it by applying a high level to the RESET pin. 91/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Power Down by the PDWN pin By applying a low level to the PDWN pin, the MSM6688/6688L is set to the power-down state, in which the frequency oscillation and all operations of internal circuits are halted. Unlike the reset operation by the RESET input, the control circuit will not be initialized by this power-down operation. The power-down operation will not affect the data in the internal control circuit and external serial registers. Therefore, this power-down operation is useful when the battery backup takes place in case of power failure. When PDWN goes to a low level during command execution, this execution of command is halted at the time that power-down operation is performed. When PDWN becomes low during one of the following operations, their respective operations will be performed after the power-down state is released (PDWN = H). (1) When the MSM6688/6688L is powered down (PDWN = L) during the record/playback operation: The record/playback operation is stopped. After the release of the power-down state, the postprocessing will be performed. The end of the postprocessing can be verified by checking the BUSY bit and RPM bit of the status register. (2) When the MSM6688/6688L is powered down (PDWN = L) during the phrase deleting operation: The phrase deleting operation is temporarily stopped and will be restarted after the release of the power-down state. The end of the phrase deleting operation can be verified by checking the BUSY bit. (3) When the MSM6688/6688L is powered down (PDWN = L) during the time the transition of the AOUT output to a DC level by LEV command is in progress: This transition operation is temporarily stopped and will be continued after the release of the power-down state. The end of the transition to a DC level can be verified by checking the BUSY bit. 92/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Record/Playback Control Modes There are four types of record/playback mode: flex record/playback, ROM playback by inputting address codes, direct record/playback, and direct ROM playback modes. A desired record/playback control mode can be selected by the command mode set in the SAMP command. Record/playback control mode Command mode Number of phrases Addressing Setting of recording time Flex record/playback Mode 0 63 Indirect addressing by phrase designation Setting by BLKWR command ROM playback by input of address code Mode 1 255 Indirect addressing by phrase designation — Direct record/playback Mode 2 64 (expandable) Direct addressing by ADRWR command Setting by ADRWR command Direct ROM playback Mode 3 As required Direct addressing by ADRWR command — 1. Flex record/playback The recording area for each phrase is indirectly specified by phrase designation (CA0-CA5, 63 phrases). The recording area for each phrase is controlled by the MSM6688/6688L, so that the address control load of the microcontroller can be reduced. The recording time is specified by the BLKWR command. During recording operation, the MSM6688/6688L searches the memory areas that are not used by other phrases and writes the voice data on them. Therefore, the phrase control by the microcontroller can be performed easily even in applications in which it is required to perform phrase deletion and re-recording frequently. 93/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. ROM playback by input of address codes The playback area of each phrase of the fixed message is indirectly specified by phrase designation (CA0-CA7, 255 phrases). The table containing the start address and stop address that indicate the playback area, sampling frequency and ADPCM bit length, is written in the index area of the serial voice ROM. 3. Direct record/playback The recording area for each phrases is specified directly by inputting the address set in the ADRWR command from the microcontroller after a desired phrase has been specified by phrase designation (CA0-CA5, 64 phrases). This means that the address control such as the allocation of memory capacity (recording time) for each phrases is performed by the microcontroller. This direct record/playback mode is suitable for the case where the number of phrases and the recording time allocated to each phrase are fixed. If the table containing the start address and stop address of each phrase is stored in the microcontroller or an external circuit, it becomes possible to perform record/playback of 65 or more phrases. 4. Direct ROM playback The playback area of each phrase for a fixed message is specified directly by inputting the address set in the ADRWR command from the microcontroller. In this case, it is required to store the table containing the start and stop addresses of each phrase, sampling frequency and ADPCM bit length in the microcontroller and the external ROM. If a serial voice ROM products for the MSM6388/MSM6588/6588L ADPCM solid state recorders are used for the MSM6688/6688L, this direct ROM playback mode is applied. 94/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Data Configuration of External Serial Registers The external RAM constitutes a virtual memory with a address space of (X addresses in the word direction) × (depth of 1K bits) through the DRAM interface (MSM6791). This virtual memory is addressable only for X addresses in the word direction. The external RAM is divided into the channel index area that stores the data for address control of each phrase and the voice (ADPCM) data area. The address space and channel index area in the flex record/playback mode are different from those in the direct record/playback mode. 1. Address space allocation of external serial registers 1.1 Address space for the flex record/playback mode In the flex record/playback mode, the total memory capacity of external serial registers is equally divided into 256 blocks that are addressable by 00h-FFh. Each block is composed of multiple words each having the depth of 1K bits. X addresses in the word direction are offset addresses in the blocks. The memory capacity of one block and the maximum address of X addresses vary depending on the total memory capacity of serial registers externally connected. RSEL2 RSEL1 Total memory capacity (Number of serial registers) Memory capacity of one block Recording time of one block Number of words of one block [Offset address] Number of initially available blocks 16 kbps 24 kbps 32 kbps L L 8M bits (1) 32K bits 2.0 seconds 1.4 seconds 1.0 seconds 32 words [00h-1Fh] 254 (FEh) L H 16M bits (2) 64K bits 4.1 seconds 2.7 seconds 2.0 seconds 64 words [00h-3Fh] 255 (FFh) H L 24M bits (3) 128K bits 8.2 seconds 5.5 seconds 4.1 seconds 128 words [00h-7Fh] 191 (BFh) H H 32M bits (4) 128K bits 8.2 seconds 5.5 seconds 4.1 seconds 128 words [00h-7Fh] 255 (FFh) 95/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L The storing method of 1K-bit ADPCM data in the Y direction varies depending on the ADPCM bit length (3-bit ADPCM or 4-bit ADPCM). (1) For 3-bit ADPCM, (3 bits × 340 samples + unused 4 bits = 1024 bits) are stored in the 1K-bit memory area. One Y address is allocated to two ADPCM data samples, so that Y addresses are addressable by 00-A9h (2) For 4-bit ADPCM, (4 bits × 256 samples = 1024 bits) are stored in the 1K-bit memory area. One Y address is allocated to two ADPCM data samples, so that Y addresses are addressable by 00-7Fh 96/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Address Space Allocation of RAM (Flex record/playback, 32M-bit) Block (256 blocks ranging from 00h to FFh, 1 block = 128K bits) 1K bits 00h 01h 8 Mbit CS1 Channel index area (64 words × 1K bits = 64K bits) X address (offset address in one block, 128 words from 00h to 7Fh, 1 word = 1K bits) 1K bits in the Y direction 00h 01h 02h 3Eh 3Fh 40h 41h 8 Mbit CS2 128 words 1 block = 128 words × 1K bits = 128K 7Eh 7Fh 80h 81h 8 Mbit CS3 7Eh 7Fh BEh BFh C0h C1h 8 Mbit CS4 00h For 3-bit ADPCM 01h Y Address 02h A7h A8h A9h 6-bits 6-bits 6-bits 6-bits 6-bits 10-bits 00h FEh FFh For 4-bit ADPCM 8-bits 01h 8-bits 7Eh 8-bits 7Fh 8-bits 97/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 1.2 Address space allocation in the direct record/playback mode In the direct record/playback mode, address control is performed by (X addresses in the word direction) × (1K bit depth in the Y direction). The maximum address of X addresses in the word direction varies depending on the total memory capacity of RAM externally connected. The header 64 words (64K bits) of the RAM are used as the channel index area. Therefore, addresses after X address 0040h can be used as the voice data area. RSEL2 RSEL1 Total memory capacity No. of words X address L L 4M bits 4K words 0000h-0FFFh L L 8M bits 8K words 0000h-1FFFh L H 16M bits 16K words 0000h-3FFFh H L 24M bits 24K words 0000F-5FFFh H H 32M bits 32K words 0000h-7FFFh The storage method of 1K-bit ADPCM data in the Y direction is identical to that for the flex record/playback mode. For 3-bit ADPCM data, the storage locations are addressable by 00h-A9h, For 4-bit ADPCM data, the storage locations are addressable by 00h-7Fh. 98/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Address Space Allocation of RAM (Direct record/playback) X address (32K words 0000h - 7FFFh, 1 word = 1K bits) 1K bits 0000h 003Fh 0040h Channel index area (64K words × 1K bits = 64K bits) ADPCM (voice) data area 1K bits in the Y direction 1 word = 1K bits 8 Mbit CS1 1FFFh 2000h 00h 8 Mbit CS2 For 3-bit ADPCM 01h Y address 02h A7h A8h A9h 6-bits 6-bits 6-bits 6-bits 6-bits 10-bits 00h 3FFFh For 4-bit ADPCM 4000h 8-bits 01h 8-bits 7Eh 8-bits 7Fh 8-bits 8 Mbit CS3 5FFFh 6000h 8 Mbit CS4 7FFFh 99/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Channel index area of serial registers 2.1 Channel index area in the flex record/playback mode In the flex record/playback mode, the channel index area for one phrase (1K bits) consists of 64K-bit address data, 704-bit user data, and 256-bit address control block table. The address data consists of the number of blocks, stop Y address, stop X address, start block, stop block, and PRED block. In the following, these areas are summarized. (1) Number of blocks: This area stores the number of blocks (recorded time) used for recording of one phrase. Address ch00 stores the number of unused blocks (available blocks). This number of blocks can be read by the BLKRD command. The recorded time for one phase and the unused capacity (available recording time) of memory can be obtained. (2) Stop Y address: This area stores the stop Y address of the phrase. A Y address location is addressable by one of 00h-A9h for 3-bit ADPCM, and by one of 00h-7Fh for 4-bit ADPCM. (3) Stop X address: This area stores the stop X address of a phrase. This X address is offset address of the block. One X address has a 1K-bit memory area. The memory capacity of one block varies depending on the number of serial registers connected externally, and addressing also varies accordingly. (4) Start block and stop block: The total memory capacity of serial registers is equally divided into 256 blocks. Addresses 00h-FFh are assigned to these blocks. The start block and stop block are stored in the start block area and stop block area, respectively. 100/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L (5) PRED block: This area stores the address of a block immediately before the stop block. In the flex record/playback mode, each recording area is controlled on a per-block basis. Therefore, a phrase is not always stored continuously in serial registers. For example, if a phrase is recorded in three blocks 03h, 04h and 07h. The PRED block stores 04h. This PRED block is used to change the stop block and stop X address for deleting a tail part of the recorded phrase. (6) User data: This user data area can be used by the user. The data can be written to and read from this area by the CHRW command. This user data area is provided independently for each phrase, so that it is useful to store the sampling frequency, ADPCM bit length and recorded time. (7) Block table: The block table is an area used for the block control. Block table 256 bits SPX0 SPX1 SPX2 SPX3 SPX4 SPX5 SPX6 SPX7 SPY0 SPY1 SPY2 SPU3 SPY4 SPY5 SPY6 SPY7 PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 1K-bit depth in the Y direction 704 bits User data 64 bits 8 bits Stop block (SPY0-SPY7) (SPX0-SPX7) (PR0-PR7) PRED block (SP0-SP7) Number of Stop Y blocks address Stop X address Number of blocks 8 bits (BL0-BL7) Stop Y address Stop X address Address data Start block Stop block 64 bits 8 bits (ST0-ST7) 8 bits ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 8 bits 16 bits Start block PRED block Lower 8 bits Unused Upper 101/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2.2 Channel index area in the direct record/playback mode In the direct record/playback mode, the channel index area for one phrase (1K bits) consists of 64-bit address data and 960-bit user data. The address data consists of the stop Y address, stop X address, start X address, and unused area. (1) Stop Y address: In the same manner as in the direct record/playback mode, the stop address can be specified by one of 00h-A9h for 3-bit ADPCM and 00h-7Fh for 4-bit ADPCM. (2) Start X address and stop X address: An X address is specified by 16 bits (15 effective bits). The 32K-word X address space can be addressed by 000h-7FFFh. (3) User data: In the same manner as in the direct record/playback mode, this user data area can be used by the user. The data can be written to and read from this area by the CHRW command. 102/167 OKI Semiconductor Depth of 1K bits in the Y direction 960 bits User data 64 bit Address data 64 bits 16 bits 16 bits 24 bits 8 bits Stop X address Unused Start X address Stop Y address Lower (SPY0-SPY7) (SPX0-SPX15) (STX0-STX15) STX0 STX1 STX2 Upper Stop Y address SPY0 SPY1 SPY2 SPY3 SPY4 SPY5 SPY6 SPY7 SPX0 SPX1 SPX2 SPX3 SPX4 SPX5 SPX6 SPX7 SPX8 SPX9 SPX10 SPX11 SPX12 SPX13 SPX14 SPX15 Stop X address Start X address STX3 STX4 STX5 STX6 STX7 STX8 STX9 STX10 STX11 STX12 STX13 STX14 STX15 FEDL6688-6688L-04 MSM6688/6688L 103/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Data Configuration of External Serial Voice ROMs The external serial voice ROMs are composed of (X addresses in the word direction) × (depth of 1K bits). The addressing is possible only for X addresses in the word direction. The maximum address of the X addresses in the word direction varies depending on the total memory capacity of the serial voice ROMs externally connected. In the ROM playback by input of address code, the header 16 words (16K bits) are used as the channel index area, so that the addresses after address 010h can be used as the voice data area. Total memory capacity (Number of ROMs) ROM playback by input of address code Direct ROM playback DTRD command Number of words X address Number of words X address 1M bits (1) 1008 words 010h-3FFh 1024 words 000h-3FFh 2M bits (2) 2032 words 010h-7FFh 2048 words 000h-7FFh 3M bits (3) 3056 words 010h-BFFh 3072 words 000h-BFFh 4M bits (4) 4080 words 010h-FFFh 4096 words 000h-FFFh The method for storing the ADPCM data of 1K bits in the Y direction is identical to that for the record/playback mode. Addressing can be made by 00h-A9h for 3-bit ADPCM and 00h-7Fh for 4-bit ADPCM. When reading data in the serial voice ROMs by the DTRD command, specify the X address and Y address and then perform the read access operation. The address locations can be specified by 000h-FFFh in the same manner as in the ROM playback. The area of 1K bits in the Y direction is equally divided into 16 of 64K bits each, so that addressing can be performed by 0h-Fh. 104/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Address Space Allocation of Serial Voice ROMs X address (4K words 000h-FFFh, 1 word = 1K bits) 1k bits 1M serial voice ROM CS1 000h 00Fh 010h Channel index area (required only for ROM playback by input of address code. 16 words × 1K bits = 16K bits) ADPCM (voice) data 1K bits in the Y direction 3FFh 400h 00h 3-bit ADPCM 1 word = 1K bits 1M serial voice ROM CS2 Y address 01h 02h A7h A8h A9h 6 bits 6 bits 6 bits 6 bits 6 bits 10 bits 00h 7FFh 800h 4-bit ADPCM 8 bits 01h 8 bits 7Eh 8 bits 7Fh 8 bits 1M serial voice ROM CS3 0h Read by DTRD command 64 bits 1h 64 bits 2h Eh Fh 64 bits BFFh C00h 1M serial voice ROM CS4 FFFh 105/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Command Description The MSM6688/6688L is controlled by 19 types of commands via D0-D3 pins constituting the data bus and WR, RD, CE, and CE control pins. The state of the MSM6688/6688L can be known by obtaining the contents of the internal status register via the data bus or the output pins. There are four command modes available: mode 0, mode 1, mode 2, and mode 3. Some commands need to set the command mode before inputting them. The command mode can be selected by setting MOD0 bit and MOD1 bit of the SAMP command. 106/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 1. Command list Code Command NOP PAUSE PLAY REC START STOP D 3 0 0 0 0 0 0 D 2 0 0 0 0 1 1 D 1 0 0 1 1 0 0 D 0 0 1 0 1 0 1 (SAMPLING FREQUENCY) (CHANNEL) (BLOCK WRITE) BLKWR 1 0 0 0 (BLOCK READ) BLKRD 1 0 0 1 (NON OPERATION) (PAUSE) (PLAYBACK) (RECORD) (START) (STOP) Command function Has no function. Suspends record/playback temporarily. Sets playback mode. Sets recording mode. Starts record/playback. Stops record/playback. Stops execution of CHRW, DTRW, DTRD, and EXT commands. Specifies the command mode and sampling frequency, in conjunction with 1 nibble following this command. Specifies a phrase, in conjunction with 2 nibbles following this command. Sets the number of recording blocks (recording time) for the phrase, in conjunction with 2 nibble following this command. Reads the number of blocks (recording time) for the phrase stored in the channel index area, in conjunction with 2 nibbles following this command. During execution of this command, the contents of the status register cannot be read. Stores the start address and the stop address to the channel index area, in conjunction with 10 nibbles following this command. Reads out the start address and the stop address stored in the channel index area, in conjunction with 10 nibbles following this command. During execution of this command, the contents of the status register cannot be read. SAMP CHAN 0 0 1 1 1 1 0 1 (ADDRESS WRITE) ADRWK 1 0 0 0 (ADDRESS READ) ADRRD 1 0 0 1 107/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Code Command D 3 1 D 2 0 D 1 1 D 0 0 (CHANNEL READ WRITE) Command function Reads out the user data stored in the channel index area or writes the user data to the channel index area by the read/write access operation following this command. Transfers data to or from the external serial registers through the data bus, by the address designation in 5 nibbles following this command and the read/write access operation. Reads the data in the external serial voice ROMs through the data bus, by the address designation in 5 nibbles following this command and the read/write access operation. Performs record/playback by inputting/outputting ADPCM data through the data bus, in conjunction with the read/write access operation. This command will be used when an SRAM or a hard disk is used for storing voice data. Does not control external serial registers and addresses. Selects the ADPCM bit length and voice triggered starting function, in conjunction with 1 nibble following this command. Deletes the phrase specified by the CHAN command. When ch00 is specified by the CHAN command, all phrases are deleted by this command. Specifies the playback output level and the transition of analog output (AOUT pin) to the DC level, in conjunction of 1 nibble following this command. This level is initialized by the RESET input. Has no function. CHRW DTRW 1 0 1 0 (DATA READ WRITE) (DATA READ) DTRD 1 0 1 0 (EXTERNAL) EXT 1 0 1 1 VDS 1 1 0 0 (VOICE DETECT SELECT) (DELETE) DEL 1 1 0 1 (LEVEL) LEV 1 1 1 0 NOP 1 1 1 1 (NON OPERATION) 108/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Command format MOD1 MOD0 Code D 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Mode 0 NOP PAUSE PLAY REC START (Flex record/ playback) STOP SAMP CHAN BLKWR BLKRD CHRW EXT VDS DEL LEV NOP Mode 1 NOP PAUSE PLAY REC START (ROM playback by input of address code) STOP SAMP CHAN BLKWR BLKRD CHRW EXT VDS DEL LEV NOP Mode 2 NOP PAUSE PLAY REC START (Direct record/ playback) STOP SAMP CHAN ADRWR ADRRD DTRW EXT VDS DEL LEV NOP Mode 3 NOP PAUSE PLAY REC START (Direct ROM playback) STOP SAMP CHAN ADRWR ADRRD DTRD EXT VDS DEL LEV NOP 0 0 0 1 1 0 1 1 109/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 3. Command data format Command NOP PAUSE PLAY REC START STOP Code HEX 0h 1h 2h 3h 4h 5h 1st nibble 2nd nibble D3 0 0 0 0 0 0 0 MOD1 D2 0 0 0 0 1 1 1 MOD0 D1 0 0 1 1 0 0 1 SA1 D0 0 1 0 1 0 1 0 SA0 Note 1-nibble command 1-nibble command 1-nibble command 1-nibble command 1-nibble command 1-nibble command 2-nibble command Command mode, sampling frequency SA1 0 0 1 1 SA0 0 1 0 1 Sampling frequency fOSC/1024 (4.0 kHz) fOSC/768 (5.3 kHz) fOSC/640 (6.4 kHz) fOSC/512 (8.0 kHz) MOD1 MOD0 SAMP 6h 0 0 1 1 0 1 0 1 Command mode Mode 0 Mode 1 Mode 2 Mode 3 Values in parentheses are for fOSC = 4.096 MHz. 1st nibble 2nd nibble 3rd nibble 0 CA3 CA7 1 CA2 CA6 1 CA1 CA5 1 CA0 CA4 3-nibble command Phrase No. CA7 CHAN 7h 0 0 0 0 … 1 1 CA6 0 0 0 0 … 1 1 CA5 0 0 0 0 … 1 1 CA4 0 0 0 0 … 1 1 CA3 0 0 0 0 … 1 1 CA2 0 0 0 0 … 1 1 CA1 0 0 1 1 … 1 1 CA0 0 1 0 1 … 1 1 Phrase No. ch00 ch01 ch02 ch03 … chFE chFF 110/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Command Code HEX 1st nibble 8h 2nd nibble 3rd nibble 1st nibble D3 1 BL3 BL7 1 BL3 BL7 1 SPY3 SPY7 SPX3 SPX7 SPX11 SPX15 STX3 STX7 STX11 STX15 1 SPY3 SPY7 SPX3 SPX7 SPX11 SPX15 STX3 STX7 STX11 STX15 D2 0 BL2 BL6 0 BL2 BL6 0 SPY2 SPY6 SPX2 SPX6 SPX10 SPX14 STX2 STX6 STX10 STX14 0 SPY2 SPY6 SPX2 SPX6 SPX10 SPX14 STX2 STX6 STX10 STX14 D1 0 BL1 BL5 0 BL1 BL5 0 SPY1 SPY5 SPX1 SPX5 SPX9 SPX13 STX1 STX5 STX9 STX13 0 SPY1 SPY5 SPX1 SPX5 SPX9 SPX13 STX1 STX5 STX9 STX13 D0 0 BL0 BL4 1 BL0 BL4 0 SPY0 SPY4 SPX0 SPX4 SPX8 SPX12 STX0 STX4 STX8 STX12 1 SPY0 SPY4 SPX0 SPX4 SPX8 SPX12 STX0 STX4 STX8 STX12 Start X address Stop X address Start X address Stop X address Note 3-nibble command Number of blocks 3-nibble command Number of blocks 11-nibble command Stop Y address BLKWR BLKRD 9h 2nd nibble 3rd nibble 1st nibble 2nd nibble 3rd nibble 4th nibble 5th nibble ADRWR 8h 6th nibble 7th nibble 8th nibble 9th nibble 10th nibble 11th nibble 1st nibble 2nd nibble 3rd nibble 4th nibble 5th nibble 11-nibble command Stop Y address ADRRD 9h 6th nibble 7th nibble 8th nibble 9th nibble 10th nibble 11th nibble 111/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Command Code HEX Ah D3 D2 D1 D0 Note 1-nibble command + read/write access + STOP command 6-nibble command + read/write access + STOP command Dummy nibble CHRW 1 0 1 0 1st nibble 2nd nibble DTRW Ah 3rd nibble 4th nibble 5th nibble 6th nibble 1st nibble 2nd nibble DTRD Ah 3rd nibble 4th nibble 5th nibble 6th nibble EXT Bh 1st nibble 2nd nibble 1 0 X3 X7 X11 X15 1 Y3 X3 X7 X11 0 1 1 0 0 0 X2 X6 X10 X14 0 Y2 X2 X6 X10 0 0 1 BIT 1 0 X1 X5 X9 X13 1 Y1 X1 X5 X9 0 1 0 VD1 0 0 X0 X4 X8 X12 0 Y0 X0 X4 X8 0 1 0 VD0 X address 6-nibble command + read access + STOP command Y address X address Dummy nibble 1-nibble command + read/write access + STOP command 2-nibble command ADPCM bit length, voice triggered starting condition Voice detection level VVDS MSM6688 MSM6688L (5 V version) (3 V version) Voice triggered Voice triggered starting disabled starting disabled ±VDD/128 ±VDD/64 (±80 mV)* (±24 mV)** ±VDD/64 ±VDD/32 (±160 mV)* (±48 mV)** ±VDD/32 ±VDD/16 (±320 mV)* (±96 mV)** BIT 0 ADPCM bit length 3 bits 4 bits VD1 0 0 1 1 VD0 0 1 0 1 VDS Ch 1 * Values in parentheses are for VDD = 5.12 V. ** Values in parentheses are for VDD = 3.072 V. 112/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Command Code HEX Dh 1st nibble 2nd nibble D3 1 D2 1 D1 0 D0 1 Note 1-nibble command DEL ch00: ch01-chFF: 1 LV1 1 LV0 Deletion of all phrases Deletion of a specified phrase 1 PN1 Playback level 0 dB 0 dB –6 dB –12 dB 0 PN0 2-nibble command Playback level, transition to DC level Transition to DC level Disabled Disabled Transition from GND to 1/2 VDD Transition from 1/2 VDD to GND LV1 LEV Eh 0 0 1 1 LV0 0 1 0 1 PN1 0 0 1 1 PN0 0 1 0 1 NOP Fh 1 1 1 1 1-nibble command 113/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 4. Relationship between record/playback control modes and commands Record/ playback mode Flex record/ playback — ∆ ⊗ ⊗ ⊗ ∆ ⊗ ⊗ ⊗ ⊗ ⊗ ∆ ∆ ∆ ROM playback by input of address code — ∆ — — ⊗ ∆ ⊗ ⊗ — ⊗ — — — — Direct record/ playback — ∆ ⊗ ⊗ ⊗ ∆ ⊗ ⊗ ⊗ ⊗ — — ⊗ ∆ Data transfer command Data transfer command Data transfer command — ⊗ ⊗ ⊗ ⊗ ⊗ ∆ ∆ — — — — — — — ∆ — ⊗ ⊗ ⊗ ∆ ∆ ∆ ∆ — ⊗ ⊗ — — — — ∆ ⊗ ⊗ ⊗ — — — — ∆ Direct ROM playback — ∆ — — ⊗ ∆ ⊗ ⊗ ⊗ ⊗ — — ⊗ — EXT command record/ playback — — ⊗ ⊗ — ⊗ ⊗ ⊗ ⊗ — — — — — Command NOP PAUSE PLAY REC START STOP SAMP Command mode Sampling frequency CHAN BLKWR BLKRD ADRWR ADRRD CHRW DTRW DTRD EXT VDS ADPCM bit length Voice triggered starting condition DEL Deletion of all phrases Deletion of a specified phrase LEV Note: ⊗: Required command ∆: Effective command —: Unnecessary command 114/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Status Register The status register used in the MSM6688/6688L is a 4-bit status register. When a low level is applied to the RD pin, the contents of the status register are output to D0-D3 pins to indicate the internal state of the MSM6688/6688L. The contents of the status register are also output to the BUSY, RPM, VPM, and NAR pins. D3 NAR D2 VPM D1 RPM D0 BUSY (1) BUSY bit The BUSY bit set to a high level indicates that the MSM6688/6688L is executing RESET operation or command processing operation. When BUSY bit is high, do not input any command from the microcontroller. While any of data read commands is being executed, the state of the BUSY bit cannot be verified by inputting the RD pulse. In this case, input a read command either after waiting a time longer than the duration of BUSY state or after verifying the end of the busy state by the BUSY pin. While the RESET operation is being executed, the BUSY bit is set to a high level, and it returns to a low level after the end of the RESET operation. After a high level pulse is applied to the RESET pin to perform the RESET operation, the BUSY bit is set to a high level during execution of the RESET operation. It goes to a low level after the end of the RESET operation. (2) RPM bit The RPM bit goes to a high level during record/playback operation. While the RPM bit is high, do not input any command except those indicated below. Otherwise, the state of the MSM6688/6688L becomes undefined. NOP, PAUSE, STOP commands, START command for release of temporary stop and playback of next phrase, CHAN command for specifying the next phrase during playback and LEV command for designation of playback output level. After a high level pulses is applied to the RESET pin to perform the RESET operation, the RPM bit goes to a low level that is the initial state. 115/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L (3) VPM bit The VPM bit goes to a high level during standby for voice after start of the voice triggered recording and during the time that record/playback is temporarily stopped by the PAUSE command. When the VPM bit is high, do not apply any command except the STOP command and the START command for release of temporary stop. Otherwise, the state of the MSM6688/6688L becomes undefined. After a high level pulse is applied to the RESET pin to perform the reset operation, the VPM bit goes to a low level that is the initial state. (4) NAR bit The NAR bit indicate the enabled or disabled state for phrase designation. When this bit is high, the phrase designation by the CHAN command is enabled. If it is desired to play back different phrases continuously during ROM playback, specify the next phrase and input the START command after verifying that the NAR bit becomes high. After a high level pulse is applied to the RESET pin to perform the reset operation, the NAR bit goes to a high level that is the initial state. 116/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L BUSY causing conditions Release of reset operation Input of 1-nibble command Input of 2-nibble command Input of 3-nibble command Input of 2-nibble or 3-nibble command data BLKRD command Input of command Output of block data ADRWR command Input of command Input of address data ADRRD command Input of command Output of address data CHRW command Input of command Input of REC command Input of write data Input of PLAY command Input of STOP command DTRW and DTRD commands Input of command Input of address (2nd to 5th nibbles) Input of address (6th nibble) Input of REC command Input of write data Input of PLAY command Input of STOP command Input of DEL command (all phrases) Input of DEL command (a specified phrase) Symbol tREX tB1 tB2 tB3 tBD BUSY state duration (Note 2) 1 ms 16 µs 16 µs 16 µs 16 µs BUSY bit verification Possible Possible Possible Possible Possible Note Input of RESET pulse NOP, PAUSE, PLAY, REC, START, STOP SAMP, VDS, LEV CHAN, BLKWR SAMP, VDS, LEV, CHAN, BLDWR tWBR tWDR tBAW tBAD tWAR tWDR tWCRW tWRC tWWD tWPL tWSP 270 µs 50 µs 270 µs 50 µs 270 µs 50 µs 770 µs 16 µs 50 µs 50 µs 50 µs Impossible Impossible Possible Possible Impossible Impossible Possible Possible (Note 1) Possible (Note 1) Impossible Possible (Note 1) Possible Possible Possible Possible (Note 1) Possible (Note 1) Impossible Possible (Note 1) Possible Possible tWRW tWA1 tWA2 tWRC tWWD tWPL tWSP tWBLA tWBL1 16 µs 16 µs 270 µs 16 µs 50 µs 50 µs 50 µs 550 ms 70 ms Notes: 1. The BUSY state can be verified by the BUSY bit when only the data write access operation is executed after the CHRW or DTRW command is input. 2. The BUSY state duration after release of RESET operation includes the oscillation startup stabilization time. This oscillation startup stabilization time is several tens of milliseconds for crystal oscillators and is several hundreds of microseconds for ceramic oscillators. 117/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Inputting the Commands To input a command or data, apply the command or data to D0-D3 pins and then apply a low level pulse (WR pulse) to the WR pin. By inputting a low level pulse (RD pulse) to the RD pin, the contents of the status register or data will be output via D0-D3 pins. The CE pin is used to enable or disable the WR pulse and RD pulse. When a low-level is applied to this CE pin, the enable state is present, so that WR and RD pulses can be accepted. When a high level is applied to this CE pin, the disable state is present, so that WR and RD pulses cannot be accepted and, at the same time, D0-D3 pins are placed in the high-impedance state. The CE pin also has the same function as the CE pin. However, when high, this CE pin gives the enable state for the WR and RD pulses, and when low, it gives the disable state. When D0-D3 pins are used exclusively for the MSM6688/6688L, CE and CE pins can be fixed to a low level and a high level, respectively. An equivalent circuit of the microcontroller interface section of the MSM6688/6688L is shown below. 118/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Status register 4 NAR VPM RPM BUSY 4 D0-D3 4 4 SEL 4 4 Data DQ LD RD pulse WR pulse 4Q RD WR CE CE PDWN RESET 119/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L The steps for inputting the commands are described below. (1) Output the contents of the status register by applying the RD pulse (namely, by applying a low level pulse to the RD pin). Verify that the BUSY bit is 0. If the BUSY bit is 1, input the RD pulse repeatedly until the BUSY bit goes to 0. The BUSY state can also be verified through the BUSY pin. (2) Set a command to D0-D3 pin and input the WR pulse. (3) In case of a 2-nibble or 3-nibble command, verify that the BUSY bit of the status register is 0 in the same way as in (1). Then, set the command data to D0-D3 pins and input the WR pulse. In this case, the WR pulse can also be input after the waiting time that is longer than the BUSY state duration, instead of verifying the BUSY bit of the status register. CE CE WR RD (I) (I) (I) (I) D0-D3 (I/O) Status output Command input Status output BUSY (O) Busy state duration Next command data can be input 120/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 1. Inputting a 2-nibble command Input RD pulse No Status output BUSY = 0? Yes Input WR pulse Verification of BUSY bit Input of the 1st nibble command Input RD pulse No Status output BUSY = 0? Yes Input WR pulse Verification of BUSY bit (or waiting for BUSY state duration) Input of the 2nd nibble data 121/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Changes of Record/Playback Conditions Record/playback condition Record/playback mode POWER ON Undefined RESET input Unchanged (Note 1) Unchanged (Note 1) Unchanged (Note 1) Unchanged (Note 1) Unchanged (Note 1) Unchanged (Note 1) Unchanged (Note 1) 0 dB Unchanged (Note 1) PDWN input Unchanged Command input REC command →Record mode PLAY command →Playback mode Set by SAMP command Set by SAMP command Set by CHAN command Set by BLKWR command Set by VDS command Set by VDS command Set by LEV command — Command mode Sampling frequency Phrase No. Number of phrase recording blocks ADPCM bit length Voice triggered level Playback level Data in serial registers Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Note: 1. RESET is performed without synchronization with the clock. When the RESET pulse is input during standby for commands, record/playback condition will not be changed. When the RESET pulse is input during execution of a command, all record/playback conditions may be changed and the data may become undefined. 122/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Setting and Confirming the Record/Playback Conditions 1. Specifying the control mode for record/playback (by the SAMP command) Specify the control mode for record/playback by setting the command mode (using MOD1 and MOD0 bits) as shown in the following table. MOD1 0 0 1 1 MOD0 0 1 0 1 Command mode Mode 0 Mode 1 Mode 2 Mode 3 Control mode for record/playback Flex record/playback ROM playback by input of address code Direct record/playback Direct ROM playback 2. Specifying the sampling frequency (by the SAMP command) Specify the sampling frequency by setting SA0 and SA1 bit data of the SAMP command. The relationship between the master oscillator frequency (fOSC), and sampling frequency (fSAMP) depends on the SA0 and SA1 bit data of the SAMP command as shown in the following table. SA1 0 0 1 1 SA0 0 1 0 1 Sampling frequency fSAMP fOSC/1024 (4.0 kHz) fOSC/768 (5.3 kHz) fOSC/640 (6.4 kHz) fOSC/512 (8.0 kHz) ( ) Values in parentheses are for fOSC = 4.096 MHz. 123/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 3. Specifying the ADPCM bit length (by the VDS command) Specify the ADPCM bit length by setting the BIT bit data of the VDS command as shown in the following table. BIT 0 1 ADPCM bit length 3 bits 4 bits 4. Specifying the voice triggered starting (by the VDS command) This MSM6688/6688L has the voice triggered starting function that starts recording when the level of voice input exceeds a preset amplitude. Using the voice activated function, the unvoiced part prior to voice detection will not be recorded, so that the memory capacity can be utilized efficiently. The unvoiced parts in the middle of recording are not eliminated. In the voice triggered starting mode, recording is started when a voice input exceeds the preset thresholds. Therefore, a consonant part with a low level may not be recorded. Voice input level (ADIN pin) 1/2VDD Upper threshold +Vvds –Vvds Lower threshold Identified as voice and recording start Start signal input 124/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Specify the enable/disable of the voice triggered starting function and the voice detection level by VD0 and VD1 bit data of the VDS command as shown in the following table. VD1 0 0 1 1 VD0 0 1 0 1 Voice detection level, Vvds MSM6688 (5 V version) Voice triggered starting disabled ±VDD/64 (±80 mV) * ±VDD/32 (±160 mV) * ±VDD/16 (±320 mV) * MSM6688L (3 V version) Voice triggered starting disabled ±VDD/128 (±24 mV) ** ±VDD/64 (±48 mV) ** ±VDD/32 (±96 mV) ** * Values in parentheses are for VDD = 5.12 V. ** Values in parentheses are for VDD = 3.072 V. During standby for voice, the VPM bit of the status register is 1. This bit returns to 0 at the start of recording after detection of voiced signal. The RPM bit is 1 during standby for voice and during recording. WR D0-D3 START command STOP command Status register RPM bit VPM bit Standby for recording Standby for voice Recording in progress Identified as voice Standby for recording When the STOP command is input during standby for voice, standby for voice will be finished and changed to standby for recording. If in the flex record/playback mode, the STOP command is input during standby for voice, the contents of the specified phrase will be deleted. WR D0-D3 START command STOP command Status register RPM bit VPM bit Standby for recording Standby for voice Standby for recording 125/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 5. Specifying a phrase (by the CHAN command) Specify a phrase by CA0-CA7 bit data of the CHAN command as shown in the following table. Phrase No. CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Flex record/ playback (Note 1) ROM playback by input of address code Disabled Direct record/ playback Direct ROM playback 0 0 0 … 0 0 0 0 … 1 1 0 0 0 … 0 0 1 1 … 1 1 0 0 0 … 1 1 0 0 … 1 1 0 0 0 … 1 1 0 0 … 1 1 0 0 0 … 1 1 0 0 … 1 1 0 0 0 … 1 1 0 0 … 1 1 0 0 1 … 1 1 0 0 … 1 1 0 1 0 … 0 1 0 1 … 0 1 ch00 ch01 ch02 ch3E ch3F ch40 ch41 … chFE chFF … Enable (63 phrases) Enable (255 phrases) Inhibit Enable (64 phrases) Enable (Note 2) Inhibit Inhibit Notes: 1. In the flex record/playback mode, ch00 cannot be used for recording/playback. This is a special phrase only used for deletion of all phrases and control of unused blocks. 2. In the direct ROM playback mode, playback will be started after transferring the address data to the channel index area of the serial registers. Therefore, it is required for direct ROM playback to use a phrase unused for record/playback operation. Normally, phrase ch3FH is used as the phrase dedicated for direct ROM playback. 126/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 6. Specifying the number of phrase recording blocks (by the BLKWR command) In the flex record/playback mode, set the number of blocks before starting the recording to specify the recording time for a phrase. In this mode, the total memory capacity of serial registers connected externally is divided equally into 256 blocks. Therefore, the memory capacity of one block varies depending on the number of serial registers connected externally. For example, when one 8M bit serial register is connected and recording is performed by 4-bit ADPCM and 8-kHz sampling, the memory capacity of one block and the recording time of one block are obtained as follows. Memory capacity of one block = 8M bits 256 = 32K bits Recording time/block = Memory capacity of one block sampling frequency × ADPMC bit length 32 × 1024 bits 8000 Hz × 4 bits = Approximately 1 second = If it is desired to make recording for 10 seconds on a phrase in this example, 10 (0Ah) phrase recording blocks are required. 127/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L The number of phrase recording blocks can be specified by the BLKWR command and is stored in the (corresponding) register in the MSM6688/6688L. The BLKWR command is enabled for command mode 0 or 1. Therefore, before inputting this BLKWR command, it is required to set the corresponding command mode using the SAMP command. BL7 0 0 0 0 … 1 1 BL6 0 0 0 0 … 1 1 BL5 0 0 0 0 … 1 1 BL4 0 0 0 0 … 1 1 BL3 0 0 0 0 … 1 1 BL2 0 0 0 0 … 1 1 BL1 0 0 1 1 … 1 1 BL0 0 1 0 1 … 0 1 Number of phrase recording blocks (HEX) Input inhibit 1 (01h) 2 (02h) 3 (03h) 254 (FEh) 255 (FFh) … 7. Reading the number of phrase recording blocks (by the BLKRD command) The number of blocks for each phrase stored in the channel index area can be read by the read access operation using the BLKRD command and two nibbles following this BLKRD command. In the flex record/playback mode, the number of blocks (namely, the recording time) of the specified phrase can be obtained. In the BLKRD command, the number of blocks is specified by a binary number consisting of BL0-BL7 in the same way as in the BLKWR command. Before inputting the BLKRD command, the command mode must be set to either mode 0 or mode 1 by using the SAMP command. (1) When ch00 phrase is specified: The number of unused blocks (or available blocks) is stored in address ch00 of the channel index area. Therefore, the unused and available memory capacity (or available recording time) can be obtained. (2) When one of ch01-ch3F is specified as a phrase: The number of blocks (or recording time) used by the specified phrase can be obtained. 128/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L BLKRD Command Flow Chart SAMP command CHAN command Setting of common mode to mode 0 or mode 1 (MOD0, MOD1) Phrase designation (CA0-CA7) 1st nibble BLKRD command 2nd nibble Wait for BUSY state duration Input RD pulse 3rd nibble Wait for BUSY state duration Input RD pulse Output of upper 4 bits of the number of blocks Output of lower 4 bits of the number of blocks Wait for BUSY state duration During execution of the BLKRD command, verification of the status register cannot be performed by input of the RD pulse. When inputting the RD pulse for the 2nd nibble or 3rd nibble or inputting the next command after the BLKRD command, input the RD pulse either after the waiting time longer than the BUSY state duration or after verifying that the BUSY status is not present via the BUSY pin. 129/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 8. Inputting/outputting the address data (by the ADRWR/ADRRD command) In the direct record/playback mode or direct ROM playback, input the start address and stop address of a phrase directly into the channel index area in the RAM by the ADRWR command. The ADRRD command is used to read the address data stored in the channel index area. The header 40 bits of each phrase of the channel index area can be accessed by the ADRWR or ADRRD command. In the flex record/playback mode, these commands can be used to change the address data for deleting the tail part of a recorded phrase. Direct record/playback and direct ROM playback D3 1st nibble 2ndnibble 3rd nibble 4th nibble 5th nibble 6th nibble 7th nibble 8th nibble 9th nibble 10th nibble 11th nibble 1 SPY3 SPY7 SPX3 SPX7 SPX11 SPX15 STX3 STX7 STX11 STX15 D2 0 SPY2 SPY6 SPX2 SPX6 SPX10 SPX14 STX2 STX6 STX10 STX14 D1 0 SPY1 SPY5 SPX1 SPX5 SPX9 SPX13 STX1 STX5 STX9 STX13 D0 * SPY0 SPY4 SPX0 SPX4 SPX8 SPX12 STX0 STX4 STX8 STX12 Start X address Stop X address Contents Command Stop Y address D3 1 BL3 BL7 SPY3 SPY7 SPX3 SPX7 SP3 SP7 PR3 PR7 0 BL2 BL6 SPY2 SPY6 SPX2 SPX6 SP2 SP6 PR2 PR6 Flex record/playback D2 D1 0 BL1 BL5 SPY1 SPY5 SPX1 SPX5 SP1 SP5 PR1 PR5 D0 * BL0 BL4 SPY0 SPY4 SPX0 SPX4 SP0 SP4 PR0 PR4 Contents Command Number of blocks Stop Y address Stop X address Stop block PRED block Note: When the address data is input by the ADRWR command in the direct ROM playback mode, the 7th nibble and the 11th nibble are dummy nibbles. Therefore, input 0h data into SPX12-SPX15 (7th nibble) and STX12-STX15 (11th nibble). 130/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ADRWR Command Flow Chart SAMP command CHAN command Setting of command mode to mode 2 or mode 3 (MOD = 1) Phrase designation (CA0-CA7) 1st nibble ADRWR command 2nd nibble BUSY = 0? Input WR pulse 3rd nibble Input of command after verification of BUSY state BUSY bit verification (or waiting for BUSY state duration or longer) Input of address data 4th nibble 10th nibble 11th nibble BUSY = 0? Input WR pulse Verification of address data 131/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ADDRD Command Flow Chart SAMP command CHAN command Setting of command mode to mode 2 or mode 3 (MOD0, MOD1) Phrase designation (CA0-CA7) 1st nibble ADRRD command 2nd nibble Wait for BUSY state duration Input RD pulse 3rd nibble Output of address data Input of command after verification of BUSY state 4th nibble 10th nibble 11th nibble Wait for BUSY state duration Input RD pulse Output of address data Wait for BUSY state duration 132/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L During execution of the ADRRD command, verification of the status register cannot be performed by input of the RD pulse. When inputting the RD pulse for the 2nd nibble to 11th nibble or inputting the next command after the ADRRD command, input the RD pulse either after the waiting time longer than the BUSY state duration or after verifying that the BUSY status is not present via the BUSY pin. 9. Specifying the playback level (by the LEV command) For playback, one of three output levels 0 dB, –6 dB and –12 dB can be selected. The playback level can be specified by LV0 and LV1 bit data of the LEV command. If the LEV command is input during playback operation, the playback level will be changed at the moment when the command is input. When the RESET pulse is input, the playback output level is set 0 dB that is the initial state. LV1 0 0 1 1 LV0 0 1 0 1 Playback level 0 dB (equal to the voice data amplitude) 0 dB (equal to the voice data amplitude) –6 dB (one-half to the voice data amplitude) –12 dB (one-fourth to the voice data amplitude) 133/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flex Record/Playback Method 1. Deleting phrases 1.1 Deleting all phrases To delete all phrases, specify ch00 by the CHAN command and input the DEL command. When all phrases are deleted in this manner, “0” data is written into ch01-ch3F addresses of the channel index area of the serial registers to place these addresses in the unrecorded state. The initial data for address control is written in ch00 address. Therefore, whenever the power is turned on, always perform the deletion of all phrases after inputting the RESET pulse. The deletion of all phrases causes the user data area ch00-ch3F to be cleared to all 0s. Note that when the data was transferred to the channel index area by the CHRW command, this data is deleted by the deletion of all phrases. Phrases No. ch00: ch01-ch3F State of the channel index area Address data Initial data User data Cleared to all 0s Cleared to all 0s Block table Initial data 1.2 Deleting a specified phrase To delete a specified phrase, specify one of ch0-ch3F by the CHAN command and input the DEL command. The deleted phrase is placed in the unrecorded state. The channel index area for the specified phrase, including the user data, is cleared to all 0s. The data stored in ch00 address for control of unused blocks is updated. Phrase deletion flow chart CHAN command ch00 ch01-ch3F: Deletion of all phrases Deletion of a specified phrase DEL command 134/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Method of recording in the flex record/playback mode 2.1 When only an 8M-bit serial register is used (1) Before starting the recording operation in the flex record/playback mode, always perform the deletion of all phrases after turning power on and resetting the MSM6688 by input of the RESET pulse. Otherwise, the address control cannot be performed correctly. (2) Input the record/playback conditions by the corresponding commands as follows. VDS command: SAMP command: CHAN command: BLKWR command: REC command: Specify the ADPCM bit length (BIT) and voice triggered starting (VD0, VD1). Set the command mode to mode 0 (MOD0 = 0, MOD1 = 0) and specify the sampling frequency (SA0, SA1). Select phrases (CA0-CA5) from one of 63 phrases ch01-ch3F. Specify the number of phrase recording blocks (BL0-BL7). Set to the recording mode (3) Input the START command to start recording (4) When the number of blocks specified by the BLKWR command is reached or when all available blocks are used for recording, recording is finished. The end of recording can be verified by the RPM bit of the status register. (5) To stop recording in the middle, input the STOP command. The contents of the block counter and the contents of the address counter at this moment are automatically stored in the channel index area as the stop block and the stop address, respectively. In this case, make sure that recording is finished by examining the RPM bit before inputting the next command. (6) To continue recording, specify the record/playback conditions to be modified by the corresponding commands and perform the steps (3)-(5). 135/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Flex Recording in the Record/Playback Mode CHAN command DEL command Specify ch00. Delete all phrases. VDS command SAMP command ADPCM bit length (BIT) Voice triggered starting (VD0, VD1) Set the command mode to mode 0 (MOD0 = 0, MOD1 = 0). Specify the sampling frequency (SA0, SA1). Select one of 63 phrases (CA0-CA5). CHAN command BLKWR command Set the phrase recording time (BL0-BL7). REC command Set the recording mode. START command Start of recording No RPM = 1? Yes RPM = 0? Yes Verify the start of recording. Input record/playback conditions to be modified by the corresponding commands. Verify the end of recording. No No Stop recording? Yes STOP command Stop of recording No RPM = 0? Yes Verify the end of recording. Yes Continue recording? No 136/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2.2 When 4M bit serial register is used This IC’s memory capacity is divided into 256 blocks for address management. This allows the connection of an 8M-bit serial register only. When connecting a 4M-bit serial register, set pins RSEL1 and RSEL2 as if only an 8M-bit serial register were connected. Then, for actual usage, the 8M-bit serial register is replaced by a 4M-bit serial register. Replacement by the 4M-bit serial register results in the occurrence of an address area prohibited from being used. Thus, the CPU must control the address area so that it is not accessed. The recording procedure is almost the same as for using only an 8M-bit serial register. Before recording, however, the number of available blocks must be determined, and a number of blocks that does not exceed that value must be set each time by the BLKWR command. The following gives the procedure for this setting. BLKRD command Read the number of remaining blocks. Calculate the number of available blocks [(Number of remaining blocks) –(number of blocks for 4M bits)] Calculated by the CPU. BLKWR command Set a value not more than the number of available blocks as the number of phrase recording blocks. The following example provides the number of blocks available when one 4M-bit serial register is connected and the erasure of all phrases is followed by the first recording. (Number of available blocks) = (number of remaining blocks) – (number of blocks for 4M bits) 4M bits = (number of remaining blocks) – ( ) memory capacity for one block 4M bits = 254 – 32K bits = 254 – 128 = 126 (7Eh) 137/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L The following table provides the memory configurations available when a 4M-bit serial register is used for flex record/playback. RSEL2 RSEL1 Serial register and corresponding CS signal Total memory capacity Memory capacity per block Number of blocks for 4M bits Initially available block (when only an 8M-bit serial register is used) CS1 CS2 CS3 CS4 L L 4 Mbit — — — 4 Mbit × 1 32 Kbit 128 (80h) 126 (7Fh) [254 (FEh)] L H 8 Mbit 4 Mbit — — 12 Mbit × 2 64 Kbit 64 (40h) 191 (BFh) [255 (FFh)] H L 8 Mbit 8 Mbit 4 Mbit — 20 Mbit × 3 128 Kbit 32 (20h) 159 (9Fh) [191 (BFh)] H H 8 Mbit 8 Mbit 8 Mbit 4 Mbit 28 Mbit × 4 128 Kbit 32 (20h) 223 (DFh) [255 (FFh)] 138/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 3. Playback method in the flex record/playback mode (1) Input the record/playback conditions by the corresponding commands as follows. VDS command: SAMP command: CHAN command: LEV command: PLAY command: Specify the ADPCM bit length (BIT). The voice triggered starting (VD0, VD1) is invalid for the playback operation. Set the command mode to mode 0 (MOD0 = 0, MOD1= 0) and specify the sampling frequency (SA0, SA1). Select one of 63 phrases ch01-ch3F (CA0-CA5). Specify the playback output level (LV0, LV1). Set to the playback mode (2) Input the START command to start the playback. The MSM6688/6688L fetches the contents of the block table and the stop address of the specified phrase from the channel index area and starts the playback operation. (3) When the contents of the address counter coincide with the contents of the stop address register, playback is finished. The end of playback is verified by the RPM bit of the status register. (4) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished by examining the RPM bit before inputting the next command. (5) To continue playback, specify the record/playback conditions to be modified by the corresponding commands and perform steps (2)-(4). 139/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Playback in the Flex Record/Playback Mode VDS command SAMP command CHAN command LEV command PLAY command ADPCM bit length (BIT) Set the command mode to mode 0 (MOD0 = 0, MOD1 = 0). Specify the sampling frequency (SA0, SA1). Select one of 63 phrases (CA0-CA5). Set playback output level (LV0, LV1) Set to the playback mode START command Start of playback No RPM = 1? Yes RPM = 0? No Yes Verify the start of playback. Input record/playback conditions to be modified by the corresponding commands. No Verify the end of playback. Stop playback? Yes STOP command STOP of playback No RPM = 0? Yes Verify the end of playback. Yes Continue playback? No This flow chart can apply to the playback operation in the direct record/playback mode, excluding that the command mode is set to mode 2 by the SAMP command and one of 64 phrases (ch00-ch3F) can be selected by the CHAN command in the direct record/playback mode. 140/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Direct Record/Playback Method 1. Recording method in the direct record/playback mode (1) Input the record/playback conditions by the corresponding commands as follows. VDS command: SAMP command: CHAN command: ADRWR command: REC command: Specify the ADPCM bit length (BIT) and voice triggered starting (VD0, VD1). Set the command mode to mode 2 (MOD = 0, MOD = 1) and specify the sampling frequency (SA0, SA1). Select one of 64 phases ch00-ch3F (CA0-CA5). Input the start address and the stop address. Set to the recording mode (2) Input the START command to start the recording. The MSM6688/6688L fetches the start address and the stop address of the specified phrase input by the ADRWR from the channel index area and stores them in the address counter and the stop address register, respectively. Then it starts recording. (3) When the contents of the address counter coincide with the contents of the stop address register, recording is finished. Verity the end of recording by the RPM bit of the status register. (4) To stop recording in the middle, input the STOP command. In this case, the contents of the address counter is automatically stored in the channel index area as a new stop address. Make sure that recording is finished by examining the RPM bit before inputting the next command. (5) To continue recording, specify the record/playback conditions to be modified by the corresponding commands and perform steps (2)-(4). 141/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Recording in the Direct Record/Playback Mode VDS command SAMP command CHAN command ADRWR command REC command ADPCM bit length (BIT) Voice triggered starting (VD0, VD1) Set the command mode to mode 2 (MOD0 = 0, MOD1 = 1). Specify the sampling frequency (SA0, SA1). Select one of 64 phrases (CA0-CA5). Input the start address and stop address. Set the recording mode. START command Start of recording No RPM = 1? Yes RPM = 0? No Yes Verify the start of recording. Input record/playback conditions to be modified by the corresponding commands. No Verify the end of recording. Stop recording? Yes STOP command Stop of recording No RPM = 0? Yes Verify the end of recording. Yes Continue recording? No 142/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Playback method in the direct record/playback mode The playback method in the direct record/playback mode is similar to that in the flex record/playback mode, excepting that in the direct playback mode, the command mode is specified to mode 2 by the SAMP command and a phrase can be selected from a total of 64 phrases (ch00-ch3F) by the CHAN command. (1) Input the record/playback conditions by the corresponding commands as follows. VDS command: SAMP command: CHAN command: LEV command: PLAY command: Specify the ADPCM bit length (BIT). The voice triggered starting (VD0, VD1) is invalid for the playback operation. Set the command mode to mode 2 (MOD = 0, MOD = 1) and specify the sampling frequency (SA0, SA1). Select one of 64 phrases ch00-ch3F (CA0-CA5). Specify the playback output level (LV0, LV1). Set the playback mode (2) Input the START command to start the playback. The MSM6688/6688L fetches the start address and the stop address of the specified phrase from the channel index area and stores them in the address counter and the stop address register, respectively. Then it starts the playback operation. (3) When the contents of the address counter coincide with the contents of the stop address register, playback is finished. The end of playback is verified by the RPM bit of the status register. (4) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished by examining the RPM bit before inputting the next command. (5) To continue playback, specify the record/playback conditions to be modified by the corresponding commands and perform steps (2)-(4). For the flow chart, refer to the flow chart of record/playback in the flex record/playback mode. 143/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L ROM Playback by Inputting Address Code 1. Method of inputting commands (1) Input the record/playback conditions by the corresponding commands as follows. SAMP command: CHAN command: LEV command: Set the command mode to mode 1 (MOD0 = 1, MOD1= 0). The sampling frequency (SA0, SA1) is invalid. Select one of 255 phrases ch01-chFF (CA0-CA7). Specify the playback output level (LV0, LV1). (2) Input the START command to start the playback. The MSM6688/6688L fetches the data of the start address, stop address, sampling frequency, and ADPCM bit length of the specified phrase from the channel index area of the serial voice ROMs and starts the playback operation. (3) When the contents of the address counter coincide with the contents of the stop address register, playback is finished. The end of playback is verified by the RPM bit of the status register. (4) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished by examining the RPM bit before inputting the next command. (5) To continue playback, specify the record/playback conditions to be modified by the corresponding commands and perform steps (2)-(4). 144/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of ROM Playback by Input of Address Code SAMP command CHAN command LEV command Set the command mode to mode 1 (MOD0 = 1, MOD1 = 0). Select one of 255 phrases (CA0-CA7). Set playback output level (LV0, LV1). START command Start of playback No RPM = 1? Yes RPM = 0? No Yes Verify the start of playback. Input record/playback conditions to be modified by the corresponding commands. No Verify the end of playback. Stop playback? Yes STOP command STOP of playback No RPM = 0? Yes Verify the end of playback. Yes Continue playback? No 145/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Continuous ROM playback The procedure for playback of different phrases such as the time signal continuously is described below. The command inputting procedure for continuous ROM playback is basically equal to that for a single phrase. In this case, during playback of a phrase, the next phrase to be played back can be specified by the NAR bit of the status register. Continuous playback can also be performed by verifying the end of playback of each phrase using the RPM, instead of use of the NAR bit. To make continuous playback using NAR bit perform the following procedure. (1) Specify a phrase by the CHAN command and input the START command to start playback. When the START command is accepted, the NAR bit of the status register goes to 0. (2) When the NAR bit is changed from 0 to 1 to indicate that the next phrase can be specified and inputted, specify the next phrase to be played back by the CHAN command and input the START command. After the START command is accepted, the NAR bit goes to 0 again. (3) In the same way as mentioned above, repeat the designation of a phrase and input of the START command verifying the state of the NAR bit. 146/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Continuous ROM Playback No NAR = 1? Yes Verify whether a phrase can be specified or not. CHAN command Specify one of 255 phrases (CA0-CA7). The specified phrase is accepted. START command No NAR = 0? Yes Verify whether playback of the specified phrase is accepted or not. Yes Next phrase to be played back? No No RPM = 0? Yes Verify the end playback. 147/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Direct ROM Playback Method A technique for ROM to be accessed directly is used when the contents of a serial voice ROM prepared for the MSM6388/6588/6588L are played back. The channel index area is not provided at the header area of serial voice ROMs. Therefore, it is required to prepare a ROM in the microcontroller or an external ROM to store the start and stop addresses, sampling frequency, and ADPCM bit length of each phrase. The start address and stop address of each phrase consists of 32 bits. These addresses are indicated in the voice address corresponding list of the serial voice ROM. For example, the addresses to provide the “Message + Cattle Voice (English)” are as shown in the following table. Voice words No.1 Message + Cattle Voice (English) Start X address STX11-STX0 000h Stop X address SPX11-SPX0 010h Stop Y address SPY7-SPY0 5Dh Sampling frequency fs 6.4 kHz ADPCM bit length 4 bits Before starting playback, the address data must be transferred to the channel index area of the status register using the ADRWR command. In this case, a phrase that is not used for record/playback must be specified for this direct ROM playback using the CHAN command. When recording a phrase in the flex record/playback mode, ch00 is inhibited to specify. Normally, ch3F address is used as the phrase dedicated for direct ROM playback. (1) Input the record/playback conditions by the corresponding commands as follows. VDS command: SAMP command: CHAN command: ADRWR command: Specify the ADPCM bit length (BIT). The voice triggered starting (VD0, VD1) is invalid for the playback operation. Set the command mode to mode 3 (MOD1 = 1, MOD0 = 1) and specify the sampling frequency (SA0, SA1). Select one of 64 phrases ch00-ch3F (CA0-CA5). Normally ch3F is used for direct ROM playback. Specify the start and stop addresses. (2) Input the START command to start the ROM playback. The MSM6688/6688L fetches the start address and the stop address of the specified phrase from the channel index area of the serial registers. Then it starts the playback operation. (3) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished by examining the RPM bit. 148/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Direct ROM Playback VDS command SAMP command CHAN command ADRWR command ADPCM bit length (BIT) Set the command mode to mode 3 (MOD0 = 1, MOD1 = 1). Specify the sampling frequency (SA0, SA1). Select one of 64 phrases (CA0-CA5). Normally, specify ch3F. Input the start address and stop address. START command Start of playback No RPM = 1? Yes RPM = 0? No Stop playback? Yes Yes Verify the start of playback. Input record/playback conditions to be modified by the corresponding commands. No Verify the end of playback. STOP command Stop of playback No RPM = 0? Yes Verify the end of playback. Yes Continue playback? No 149/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Stopping Record/Playback Temporarily (by the PAUSE Command) The record/playback operation in progress can be stopped temporarily by inputting the PAUSE command. The record/playback operation stopped using the PAUSE command can be restarted by inputting the START command. During temporary stop state, the VPM bit of the status register is 1 and the RPM bit keeps 1. If the START command is input to restart the recording operation that is temporarily suspended by the PAUSE command in the voice reiggered starting mode, the recording will be started immediately even in the state of silence. The PAUSE command is invalid during record/playback standby state, temporarily stopped state, and standby state for voice. WR D0-D3 Status register RPM bit VPM bit Standby Record/playback Temporarily stopped Record/playback Standby Immediately restarted even in case of voice triggered starting START command PAUSE command START command STOP command When the STOP command is input during temporarily stopped state, the record/playback operation is finished and the MSM6688/6688L is placed in the standby state. WR D0-D3 Status register RPM bit VPM bit Standby Record/standby Temporarily stopped Standby START command PAUSE command STOP command 150/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Transferring Data to/from External Memories 1. Method of transferring data to/from external serial registers (by the CHRW command) The MSM6688/6688L can transfer data to/from the user area in the channel index area of external RAM using the CHRW command. Before starting this data transfer operation, a desired phrase must be specified using the CHAN command. The memory capacity for each phrase is 704 bits (176 nibbles) in the flex record/playback mode and 960 bits (240 nibbles) in the direct record/playback mode. The read/write operation must be performed for the data that does not exceed this memory capacity per phrase. The contents of the user area for a specified phrase or for all phrases will be cleared to all 0s (0h data) using the CHAN and DEL commands. The following shows the procedure for inputting the CHRW command. (1) Set the command mode to mode 0 or mode 1 (MOD1 = 0) using the SAMP command. (2) Specify a phrase using the CHAN command. (3) After inputting the CHAN command, wait for BUSY state duration. The end of the BUSY state duration can also be verified by the BUSY bit of the status register. (4) To write data, input the REC command and then input the data to be written by applying the WR pulse. It is required to wait for the busy state duration between the contiguous WR pulses. When the data writing operation is performed by inputting a single input of the CHRW command, the state of the BUSY bit of the status register can be verified by inputting the RD pulse. When the data read operation is performed with the data write operation, the state of the BUSY bit cannot be verified by inputting the RD pulse. (5) When reading data, wait for the BUSY state duration after inputting the PLAY command and then input the RD pulse. With this operation, 4-bit data will be output via the data bus. (6) To continue the data read or write operation, specify the read or write mode using the PLAY or REC commands. (7) To stop the data read/write operation, input the STOP command. After waiting for the BUSY state duration, the next command can be input. 151/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Data Transfer Using the CHRW Command SAMP command CHAN command CHRW command Wait for BUSY state duration No Set the command mode to mode 0 or mode 1 (MOD1=0). Specify one of 64 phrases (CA0-CA5). Data write? Yes (Data write) REC command Wait for BUSY state duration Input WR pulse Wait for BUSY state duration Data input (Data read) PLAY command Wait for BUSY state duration Input RD pulse Data output Yes Continue data transfer? No STOP command Wait for BUSY state duration 152/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Method of transferring data to and from external RAM (by the DTRW command) The data transfer to/from external RAM is performed using the DTRW command. After inputting the DTRW command, specify an address to be accessed for data read/write. The transfer of each 4-bit data is performed from the starting nibble of the specified address. For the address space, refer to Section 1.2 “Address space allocation in the direct record/playback mode” in “Data Configuration of External RAM.” The address designation can be made only in the X direction and random address designation cannot be made in the Y direction to select an arbitrary address in the Y direction. With the input of a single DTRW command, continuous read/write operation can be made in the range of addresses 8M bit (CS1, CS2, CS3, CS4). When the read/write operation is extended to two or more 8M bits (CS1, CS2, CS3, CS4), it is necessary to stop temporarily the read/write operation each time the operation is finished for one serial register, and set the address for another serial register using the DTRW command. (1) Set the common mode to mode 2 (MOD0 = 0, MOD1 = 1). (2) Input the DTRW command. (3) Specify the X address in a serial register by inputting the WR pulse five times. Wait for the BUSY state duration. The BUSY state can be verified by examining the state of the BUSY bit of the status register. The 2nd nibble of the DTRW command is a dummy nibble. Always input 0h data into the 2nd nibble. (4) For data writing, input the REC command and input the data to be written by inputting the WR pulse. Wait for the BUSY state duration between the contiguous WR pulses. To make the data write operation by a single input of the DTRW command, the state of the BUSY bit can be verified by inputting the RD pulse. When data write and data read operations are performed jointly, the state at the BUSY bit cannot be verified using the RD pulse. (5) To read data, input the PLAY command and then input the RD pulse after waiting for the BUSY state duration. With this operation, 4-bit data will be output via the data bus. (6) To continue data read/write operation, specify the read or write mode using the PLAY or REC command and make data transfer operation. (7) To finish the data read/write operation, input the STOP command. After waiting for the BUSY state duration, the next command can be input. 153/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Data Transfer Using the DTRW Command SAMP command DTRW command Input dummy nibble (2nd nibble) Input X address (3rd nibble) Input X address (4th nibble) Input X address (5th nibble) Input X address (6th nibble) Wait for BUSY state duration No Specify the command mode to mode 2 (MOD0 = 0, MOD1 = 1). (0, 0, 0, 0) (X0, X1, X2, X3) (X4, X5, X6, X7) (X8, X9, X10, X11) (X12, X13, X14, X15) Data write? Yes (Data write) REC command Wait for BUSY state duration Input WR pulse Wait for BUSY state duration Data input (Data read) PLAY command Wait for BUSY state duration Input RD pulse Data output Yes Continue data transfer? No STOP command Wait for BUSY state duration 154/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 3. Method of reading data from external serial voice ROMs (by the DTRD command) The data from external serial voice ROMs can be read using the DTRD command. After inputting the DTRD command, specify the address to be read. The data is read in groups of 4 bits from the specified address. For the address space, refer to “Data Configuration of External Serial Voice ROMs.” The data can be addressed on a 64-bit basis. With the input of a single DTRD command, continuous read/write operation can be made in the range of addresses assigned to the same serial voice ROM. When the read/write operation is extended to two or more serial voice ROMs, it is necessary to stop temporarily the read/write operation each time the operation is finished for the serial voice ROM, and set the address for another serial voice ROM using the DTRD command. The following shows the procedure for inputting the DTRD command. (1) Set the command mode to mode 3 (MOD0 = 1, MOD1 = 1). (2) Input the DTRD command. (3) Specify the X address and Y address of the serial voice ROM by inputting the WR pulse five times. Then, wait for the BUSY state duration. The 6th nibble is a dummy nibble. Always input 0h data into this 6th nibble. (4) Input the PLAY command and wait for the BUSY state duration. Then, input the RD pulse, so that 4-bit data will be output via the data bus. (5) To continue data read operation, perform the data read operation inputting the PLAY command and RD pulse in the same way as mentioned above. (6) To finish the data read operation input the STOP command. After waiting for the BUSY state duration, the next command can be input. 155/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Data Read Using the DTRD Command SAMP command DTRD command Input Y address (2nd nibble) Input lower bits of X address (3rd nibble) Input middle 4 bits of X address (4th nibble) Input upper 4 bits of X address (5th nibble) Input dummy nibble (6th nibble) Wait for BUSY state duration Specify the command mode to mode 3 (MOD0 = 1, MOD1 = 1). (Y0, Y1, Y2, Y3) (X0, X1, X2, X3) (X4, X5, X6, X7) (X8, X9, X10, X11) (0, 0, 0, 0) PLAY command Wait for BUSY state duration Input RD pulse Wait for BUSY state duration Yes Continue to read data? No STOP command Wait for BUSY state duration Data read 156/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Record/Playback by Inputting/Outputting Voice Data via Data Bus When SRAMs (static RAMs) or other hardware memory products are used to store voice data, the record/playback operation will be performed by using the EXT command. In the case of the record/playback using the EXT command, voice data is directly input or output via the data bus in synchronization with the sampling frequency. In this record/playback mode, the address control and the control of external RAM and serial voice ROMs are not performed. Therefore, the microcontroller performs the recording time control and address control. In this mode, temporary stop of record/playback operation by the PAUSE command and the voice triggered starting cannot be performed. 1. Method of recording using the EXT command (1) Input the record/playback conditions using the corresponding commands as shown below. VDS command: SAMP command: REC command: Set the ADPCM bit length (BIT). Specify the disabled state of voice triggered starting (VD0 = 0, VD1 = 0). Specify the sampling frequency (SA0, SA1). The command mode (MOD0, MOD1) is invalid. Set to the recording mode The sampling frequency clock is output via the MON pin. (2) Input the EXT command to start the recording. (3) When the MON pin goes high, input the RD pulse to fetch the ADPCM data from the external memory via the data bus. At that time, input the RD pulse to satisfy time tERD from rise of MON to rise of the RD pulse. In the case of 3-bit ADPCM, the upper 3 bits (D3-D1 pins) are valid and the lower 1 bit (D0 pin) is invalid. (4) Store the ADPCM data into the external memory such as SRAMs. (5) Repeat steps (3) and (4) to continue the recording operation. (6) Input the STOP command to stop the recording operation. Until the STOP command is input, the recording operation will be continued without the limit for the recording time. When the MON pin becomes “H” level, input the RD pulse to fetch the ADPCM data, and input the STOP command to satisfy time tESP from rise of MON to input of the STOP command. (7) During recording by the EXT command, the contents of the status register cannot be verified by the RD pulse. Therefore, after inputting the STOP command, wait for the BUSY state duration and then input the next command. 157/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Recording Using the EXT Command SAMP command VDS command REC command EXT command Specify the sampling frequency (SA0, SA1). Specify the ADPCM bit length (BIT). Set to the recording mode Start the recording by EXT command. Detection of the rising edge of the pulse at MON output pin Input the RD pulse Store the ADPCM data into memory Yes Continue recording? No STOP command Wait for BUSY state duration Fetch ADPCM data from memory. Store the ADPCM data into an external memory such as SRAM. End of recording by EXT command 158/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. Method of playback using the EXT command (1) Input the record/playback conditions using the corresponding commands as shown below. VDS command: SAMP command: PLAY command: Set to the ADPCM bit length (BIT) specified for recording Voice triggered starting becomes invalid. Specify the sampling frequency (SA0, SA1). The command mode (MOD0, MOD1) is invalid. Set to the playback mode (2) Input the EXT command to start the playback. The sampling frequency clock is output via the MON pin. (3) When the MON pin goes high, the ADPCM data is ready to be fetched from an external memory such as an SRAM. (4) Input the WR pulse to fetch the ADPCM data from the external memory via the data bus. At that time, input the WR pulse to satisfy time tEWR from rise of MON to rise of the WR pulse. In the case of 3-bit ADPCM, the upper 3 bits (D3-D1 pins) are valid and the lower 1 bit (D0 pin) is invalid. (5) Repeat steps (3) and (4) to continue the playback operation. (6) Input the STOP command to stop the playback operation. When the MON pin becomes “H”, input the WR pulse, input the ADPCM data, and input the STOP command to satisfy time tESP from rise of MON to input of the STOP command, and interval tWE1 between the WR pulse and the STOP command pulse. Note: Input the ADPCM data beginning with the top of a phrase every sampling period sequentially. If the ADPCM data is input beginning with the second or following part of a phrase or with data missing, normal (playback) waveforms cannot be regenerated. 159/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Flow Chart of Playback Using the EXT Command SAMP command VDS command PLAY command EXT command Specify the sampling frequency (SA0, SA1). Specify the ADPCM bit length (BIT). Set to the playback mode Start the playback by EXT command. Detection of the rising edge of the pulse at MON output pin Read ADPCM data from memory Input the WR pulse Write the ADPCM data. Yes Continue playback? No STOP command Stop the playback by EXT command. 160/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L Suppression of Pop Noise at AOUT Output (by the LEV Command) The MSM6688/6688L has a on-chip pop noise suppression circuit to prevent pop nose from being generated due to sharp changes of the DC level of the analog output (at the AOUT pin). The enabled or disabled state of this pop noise suppression circuit can be selected using the ACON pin. When the ACON pin is low, this circuit is disabled and when high, this circuit is enabled. 1. When the POP noise suppression circuit is disabled (ACON = low) When the RESET pin is high, the DC level at the AOUT pin is the ground level, and when the RESET pin is low, the DC level at the AOUT pin is the 1/2 VDD level. Each time the state of the RESET pin is changed, the DC level is changed sharply and pop noise is generated. RESET 1/2 VDD level AOUT GND level Pop noise Power down Standby Record/playback Standby GND level Pop noise Power down 161/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L 2. When the POP noise suppression circuit is enabled (ACON = high) The transition of the DC level at the AOUT (analog output) pin is controlled using the LEV command. When the RESET pulse (low) is applied to the RESET pin, the DC level at the AOUT output pin goes to the ground level. If the pop noise suppression circuit is activated using the PN0 and PN1 bits of the 2nd nibble of the LEV command, the DC level at the AOUT output pin will be changed from the ground level to the 1/2 VDD level or from the 1/2 VDD level to the ground level slowly to prevent pop noise from being generated. Before starting the record/playback operation, always set the DC level at the AOUT pin to the 1/2 VDD level using the LEV command. When enabling the DC level transition function by the LEV command, first specify the playback mode by the play command and then input the LEV command. PN1 0 0 1 1 PN0 0 1 0 1 DC level transition Disabled Disabled Transition from ground to 1/2 VDD Transition from 1/2 VDD to ground RESET 1/2 VDD level AOUT GND level GND level Power down Record/playback Transition LEV command Power down Transition LEV command 162/167 DVDD DVDD’ AVDD SADX VCC SAD SADX VCC SADX SADX OKI Semiconductor MSM6685A SAS SAS SADY SADY SAS SAS SASX MSM6596A-XXX SASY TAS TAS RWCK RDCK MSM6685A MSM6685A MSM6685A D3 D2 D1 D0 SADY RD WR CE APPLICATION CIRCUIT 4.096 MHz Speaker drive amplifier MICROCONTROLLER RESET DI/O DIN DOUT DROM DOUT TEST CS1CS2 VSS 2M SERIAL VOICE ROM MSM6596A-XXX PDWN TEST TEST TAS RWCK WE TAS TAS RWCK RWCK WE WE DI/O MCUM RSEL1 RSEL2 CE TEST NC CS VSS 8M SERIAL REGISTER DROM TEST CS1 ACON TEST CS2 CS3 CS4 BUSY RPM VPM MIN MOUT ADPCM SOLID-STATE RECORDER IC MSM6688/6688L XT LIN XT Circuit Diagram 1: Application circuit in microcontroller interface mode with 8M bit serial registers and 2M bit serial voice ROMs MON NAR LOUT AMON FIN FOUT ADIN AOUT SGC FEDL6688-6688L-04 MSM6688/6688L DGND AGND SG + + The circuit diagram 1 shows an application circuit example where the MSM6688/6688L is used in the microcontroller interface mode and four 8M bit serial registers and two 2M bit serial voice ROMs are connected. 163/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L PACKAGE DIMENSIONS (Unit: mm) QFP56-P-910-0.65-2K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.43 TYP. 4/Nov. 28, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 164/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L (Unit: mm) TQFP64-P-1010-0.50-K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.26 TYP. 4/Oct. 28, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 165/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L REVISION HISTORY Document No. E2D0026-39-23 Date Feb. 1999 Page Previous Current Edition Edition ― 28 ― 28 81 82 Third edition Description FEDL6688-6688L-04 Mar. 12, 2002 81 82 Changed contents of the tables for ceramic oscillators 166/167 FEDL6688-6688L-04 OKI Semiconductor MSM6688/6688L NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 167/167