MSM6698

E2B0030-27-Y2 ¡ Semiconductor ¡ Semiconductor MSM6698 80-DOT COMMON DRIVER This version: Nov. 1997 MSM6698 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM6698 is a dot matrix LCD common driver. Fabricated in CMOS technology, the device consists of an 80-bit bi-directional shift register, 80-bit level shifter, and 80-bit 4-level driver. The MSM6698 is equipped with 80 LCD output pins. By connecting more than two MSM6698s in series, this LSI is applicable to a wide LCD panel. FEATURES • • • • • Logic supply voltage : 2.7 to 5.5 V LCD drive voltage : 18 to 28 V Applicable LCD duty : 1/64 to 1/240 Interface with MSM6599B (80-dot segment driver) Package: 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name: MSM6698GS-K) 1/8 ¡ Semiconductor MSM6698 BLOCK DIAGRAM O1 O2 V1R V2R V5R VEER O79O80 V1L V2L V5L VEEL 80-BIT 4-LEVEL DRIVER VDD VEE DF DISP OFF 80-Bit LEVEL SHIFTER VDD VSS SHL IO1 CP VDDR/L VSS 80-Bit BIDIRECTIONAL SHIFT REGISTER IO80 Note: VDDR/L indicates an abbreviation of VDDR and VDDL. 2/8 ¡ Semiconductor MSM6698 PIN CONFIGURATION (TOP VIEW) O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 O80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 O50 99 O49 98 O48 97 O47 96 O46 95 O45 94 O44 93 O43 92 O42 91 O41 90 O40 89 O39 88 O38 87 O37 86 O36 85 O35 84 O34 83 O33 82 O32 81 O31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 V1L V2L V5L VEEL VDDL NC IO80 DF NC CP IO1 NC DISP OFF VSS SHL VDDR VEER V5R V2R V1R NC : No connection 100-Pin Plastic QFP 3/8 ¡ Semiconductor MSM6698 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage (1) Power Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VDD – VEE *1 VI TSTG Condition Ta = 25°C Ta = 25°C Ta = 25°C — Rating –0.3 to +6.5 0 to 30 –0.3 to VDD + 0.3 –55 to +150 Unit V V V °C *1 V1 > V2 > V5 > VEE, VEE + 10V ≥ V5 >VEE, VDD ≥ V1 > V2 ≥ VDD – 10V, VDD = VDDR = VDDL, V1 = V1R = V1L, V2 = V2R = V2L, V5 = V5R= V5L, VEE = VEER= VEEL RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage (1) Power Supply Voltage (2) Operating Temperature Symbol VDD VDD – VEE *1 Top Condition — No load During LCD drive — Range 2.7 to 5.5 14 to 28 18 to 28 –20 to +75 Unit V V V °C *1 V1 > V2 > V5 > VEE, VEE + 7V ≥ V5 >VEE, VDD ≥ V1 > V2 ≥ VDD – 7V, VDD = VDDR = VDDL, V1 = V1R = V1L, V2 = V2R = V2L, V5 = V5R= V5L, VEE = VEER= VEEL 4/8 ¡ Semiconductor MSM6698 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 to 5.5V, Ta = –20 to +75°C) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage ON Resistance Logic Supply Current LCD Supply Current Input Capacitance Symbol VIH *1 VIL *1 IIH IIL Condition — — Min. 0.8VDD VSS — — VDD – 0.4 — *3 — — — — Typ. — — — — — — — — — — Max. VDD 0.2VDD 1 –1 — 0.4 2.0 50 300 — Unit V V mA mA V V kW mA pF *1 VI = VDD, VDD = 5.5V *1 VI = 0V, VDD = 5.5V VOH *2 IO = –0.2mA, VDD = 2.7V VOL *2 IO = 0.2mA, VDD = 2.7V RON *4 ISS IEE CI VDD – VEE = 25V | VN – VO | =0.25V fCP = 28kHz, VDD = 3.0V VDD – VEE = 25V, No load f = 1MHz *1 Applicable to CP, IO1, IO80, SHL, DF, DISP OFF. *2 Applicable to IO1, IO80. *3 VN = VDD to VEE, V2 = 1/16 (VDD – VEE), V5 = 15/16 (VDD – VEE), VDD = V1, VDD = 4.5V VDD = VDDR = VDDL, V1 = V1R = V1L, V2 = V2R = V2L, V5 = V5R = V5L, VEE = VEER = VEEL *4 Applicable to O1 to O80 Switching Characteristics Parameter "H", "L" Propagation Delay Time Clock Frequency CP Pulse Width Data Setup Time IO1 (IO80) Æ CP Data Hold Time CP Æ IO1 (IO80) Rise / Fall Time of CP Symbol tPLH, tPHL fCP tWCP tSETUP tHOLD tr (CP), tf (CP) (VDD = 2.7 to 5.5V, Ta = –20 to +75°C, CL = 15pF) Condition — — — — — — Min. — — 63 100 100 — Typ. — — — — — — Max. 3 1 — — — 20 Unit ms MHz ns ns ns ns Note1: When display control by the DISPOFF pin is performed, CP rise and fall time must be £ 1 ms. tWCP 0.8VDD 0.8VDD tSETUP 0.2VDD tHOLD tf(CP) tr(CP) 0.8VDD 0.2VDD CP IO1 (IO80) 0.8VDD 0.2VDD tPLH (tPHL) IO80 (IO1) 0.8VDD 0.2VDD 5/8 ¡ Semiconductor MSM6698 FUNCTIONAL DESCRIPTION Pin Functional Description • IO1, IO80, SHL IO1 and IO80 are I/O pins of the 80-bit bi-directional shift register. The shift direction can be selected by the SHL pin. Set the SHL pin to "H" or "L" level during power-on. Table 1 gives functions of IO1, IO80, and SHL. Table 1 SHL Shift direction I/O Pins IO1 L O1 Æ O80 IO80 output Input, output Input Function The scanning data from the LCD controller LSI is input into IO1 synchronized with the clock pulse. was input into IO1 is output from IO80 with 80-bit delay, synchronized with the clock pulse. IO80 H O80 Æ O1 IO1 output Input The scanning data from the LCD controller LSI is input into IO80 synchronized with the clock pulse. was input into IO80 is output from IO1 with 80-bit delay, synchronized with the clock pulse. *1 Shift register contents output pin. The scanning data which *1 Shift register contents output pin. The scanning data which *1 The combination of the scanning data, IO1 or IO80, and the LCD driving output, O1 - O80, is shown in the table below. Scanning data "H" "L" LCD driving output Select level (V1, VEE) Non-Select level (V2, V5) 6/8 ¡ Semiconductor MSM6698 • CP This is a clock pulse input pin of the 80-bit bidirectional shift register. Scan data is shifted at the falling edge of a clock pulse. • DF This is an alternate signal input pin for LCD driving, which generally inputs a frame inversion signal. • DISP OFF This is an input pin to control the output pins O1 to O80. During low signal input, signals on the V1 level are output from the output pins O1 to O80. See the Truth Table. • O1 to O80 4-level driver outputs of this IC device, directly corresponding to each bit of the bidirectional shift register. Any of four levels V1, V2, V5, and VEE is selected and output combining the DF signal with shift register data (see the Truth Table). These outputs are connected to the Common side on the LCD panel. • VDDR, VDDL, VSS These are power supply pins of this IC. Both the VDDR and VDDL pins are normally 2.7 to 5.5 V. VSS is a grounding pin, which is normally 0 V. • V1L, V2L, V5L, VEEL, V1R, V2R, V5R, VEER These are LCD drive bias voltage pins. The V1 pin may be separated from the VDD pin. Bias power is supplied from an external source. Truth Table DF L L H H ¥ Shift register data L H L H ¥ DISP OFF H H H H L Driver Output (O1 to O80) V2 VEE V5 V1 V1 ¥ : Don't care NOTES ON USE (when turning power ON and OFF) The LCD drivers of this IC requires a high voltage. When a high voltage is applied to them with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-ON and power-OFF sequences. When turning power ON: First turn on the logic circuits, then the LCD drivers, or turn on both of them at the same time. When turning power OFF: First turn off the LCD drivers, then the logic circuits, or turn off both of them at the same time. 7/8 ¡ Semiconductor MSM6698 PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 8/8