MSM6948

E2A0034-16-X1 ¡ Semiconductor MSM6948/6948V ¡ Semiconductor 1200 bps Single Chip MSK Modem This version: Jan. 1998 MSM6948/6948V Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM6948/6948V is a single chip MSK (Minimum Shift Keying) modem which is fabricated by Oki’s low power consumption CMOS silicon gate technology. The demodulator receives the data to be transmitted (SD) synchronized with the transmit timing clock (ST) generated by the on-chip clock generator. The signal, which is modulated by MSK method, is output. The demodulator converts the received MSK signal to the received data (RD) by means of a delay detection technique after limiting the band of the received MSK signal. This signal is input to the digital PLL and the re-generated timing clock (RT) is output from the demodulator, synchronized with the RD. FEATURES • Signal power supply: +5 V • On-chip SCF (Switched Capacitor Filter) • The transmit filter can be also used as voice splatter filter. • The receive timing re-generator has two different lock-in time performance options to be chosen from. • Built-in crystal oscillation circuit. • Small number of external components for easy application. • Wide application-wireless data equipment, MCA system. • Low power consumption CMOS. • Package options: 18-pin plastic DIP (DIP18-P-300-2.54) (Product name: MSM6948RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6948GS-K) 1/13 ¡ Semiconductor MSM6948/6948V BLOCK DIAGRAM ST SD ME TI SH CF RT Timing Re-generator RD VDD CT *2 Power ON Reset Signal Ground AG X1 X2 *1 Post Detection Filter *2 NC (MSM6948V) DG Clock Generator SG PDF *1 Delay Detector LIM RC LPF Receive BPF RC LPF AI Modulator RC LPF Transmit LPF RC LPF AO FT MCK 2/13 ¡ Semiconductor MSM6948/6948V PIN CONFIGURATION (TOP VIEW) X1 1 X2 2 *MCK 3 ME 4 SD 5 ST 6 SG 7 AG 8 DG 9 18 VDD 17 F T 16 CT 15 CF 14 RT 13 RD 12 AI 11 AO 10 TI X1 1 X2 2 *MCK 3 ME 4 (NC) 5 SD 6 (NC) 7 (NC) 8 ST 9 SG 10 AG 11 DG 12 24 VDD 23 FT 22 CT 21 CF 20 (NC) 19 RT 18 (NC) 17 (NC) 16 RD 15 AI 14 AO 13 TI 18-Pin Plastic DIP 24-Pin Plastic SOP *NC (MSM6948V) NC : No connect pin 3/13 ¡ Semiconductor MSM6948/6948V PIN DESCRIPTION Name X1 X2 *MCK Description Crystal connection pins. A 3.6864 MHz crystal shall be connected. When an external clock is applied for MSM6948's oscillation source, it has to be input to X2. In this case, X2 has to be AC-coupled by the capacitor of 200 pF. X1 shall be left open. 3.6864 MHz ±0.02% clock output. This can be used for other devices under limited load conditions. When digital "1" is put on this pin, MSK modulator output is connected to the input of transmit LPF. When digital "0" is put on, the input of transmit LPF is connected to TI that is voice signal input. The data put on ME terminal is synchronized with the rising edge of ST and input to internal logic as a control data. The rising edge of this synchronized data resets MSK modulator. Transmit data input. The data on this pin is synchronized with the rising edge of ST and input to MSK modulator as an actual transmit data. SD SD ST MSK Modulated Data ST is synchronizing signal used for ME and SD. This is made from master clock and is usually 1200 Hz. Built-in analog signal ground. The DC voltage is approximately half of VDD, so the analog signals of AI, AO, and TI interfaces with peripheral circuits which must be implemented by AC-coupling. To make this voltage source impedance lower and ensure the device performance, it is necessary to put a bypass capacitor on SG in close physical proximity to the device. Analog ground. This pin should be common with DG at the system ground point as close as possible. SD 50% SD tsetup tsetup; Min. 300 ns thold ; Min. 300 ns 50% thold ME ST SG AG *NC : MSM6948V 4/13 ¡ Semiconductor MSM6948/6948V Name DG Description Digital ground. This pin should be common with AG at the system ground point as close as possible. Voice signal input. The signal input to this pin can be sent out to AO through the transmit LPF, the characteristics of which, gives the splatter filter for voice band signal. When this function is used, digital "0" must be input to ME. TI is biased internally to SG with about 100 kW. Transmit analog signal output. According to the control data on ME and FT, AO is set to various state as an output terminal as follows. FT "1" "1" "0" "0" ME "1" "0" "1" Power Down "0" Transmit LPF Power On State of AO The output of Transmit LPF MSK Signal Voice Signal TI The Output of Receive BPF (Used for Device Test Only) No-signal Output (DC-biased to SG) AO TI Modulator Power down Transmit LPF SG + – AO SD Receive BPF AI The state when FT and ME = "0" is shown above. When the input digital data on FT changes to "1" from "0", AO remains to be connected to SG during about 12 ms and after that, and AO is switched to transmit LPF. This delay time prevents AO from outputting meaningless signal during transient time from power down to on of LPF. AI Receive analog signal input. AI is biased internally to SG with about 100 kW same as TI. Receive BPF and demodulator extract the information in this signal and convert it into a serial data stream at RD output. 5/13 ¡ Semiconductor MSM6948/6948V Name RD Description Demodulated serial data output. This data is synchronized with the re-generated timing clock RT. Receive data timing clock output. This signal is re-generated by internal digital PLL. Synchronizing to falling edge of RT, RD is output. RT RT RD Delay time (RT Æ RD) < 300 ns Receive data timing clock is re-generated by digital PLL of which phase correcting speed can be selected with CF. When a digital "1" is put on CF and phase difference between receive data timing and RT is more than 22.5 degree, phase correcting speed is high. In this case, as the phase difference enters within 22.5 degrees, that speed changes to low immediately. When digital "0" is input to CF, phase correcting speed of PLL remains low regardless of the phase difference. Usually, CF is connected to digital "1". PLL's lock-in characteristics can be selected with CT. When digital "1" is put on CT, PLL requires max. 50-bit alternative data pattern. On the other hand, when digital "0" is input to CT, PLL can be locked in below 18-bit data. CF CT Equipment Personal/MCA wireless terminals MCA wireless bases CT "1" "0" FT Control signal for the internal connection of AO. Refer to column AO. When digital "0" is input to this pin, transmit LPF enters in power down mode, but the output buffer operational amplifier remains active. +5 V power supply. This device is sensitive to supply noises as switched capacitor techniques are utilized. Bypass capacitors of more than 2.2 mF between VDD and AG, and between VDD and DG are indispensable to ensure the performance. VDD 6/13 ¡ Semiconductor MSM6948/6948V ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage *1 Digital Input Voltage *2 Operating Temperature Storage Temperature Symbol VDD VIA VID Top TSTG — — Condition Ta = 25°C With respect to AG and DG Rating –0.3 to 7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –25 to 70 –55 to 150 °C V Unit *1 TI, AI *2 ME, SD, CF, CT, FT RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Crystal Resonant Frequency Data Speed C1 C2, C6 C3 C4 C5 Frequency Deviation Crystal Symbol VDD AG, DG Top fX' TAL TS — — — — — — — — — Condition With respect to AG and DG — — — — — — — RLX ≥ 100 kW — 25 ±5°C At –40°C to +85°C — — Min. 4.75 — –25 3.6860 — — — — — — –100 –100 — — Typ. 5 0 25 3.6864 1200 2.2 0.1 0.047 0.01 0.047 — — — 16 Max. 5.25 — 70 3.6868 — — — — — — +100 +100 100 — Unit V °C MHz bit/sec mF Temperature Characteristics Equivalent Series Resistance Load Capacitance ppm W pF 7/13 ¡ Semiconductor MSM6948/6948V ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 5 V ±5%, Ta = –25°C to 70°C) Parameter Power Supply Current Oscilating Frequency Input Leakage Current *1 Input Voltage *1 Output Voltage *2 Output Voltage *3 Symbol IDD fMCK IIL IIH VIL VIH VOL1 VOH1 VOL2 VOH2 Condition Normal Operating Mode fX'TAL = 3.6864 MHz ±0.01% VIN = 0 V VIN = VDD — — IOL = 1.6 mA IOH = 400 mA RL > 50 kW CL < 20 pF Min. — 3.6857 –10 –10 0 2.2 0 0.8VDD 0 0.6VDD Typ. 3 3.6864 — — — — — — — — Max. 6 3.6871 10 10 0.8 VDD 0.4 VDD 0.4 VDD V Unit mA MHz mA *1 ME, SD, CF, CT, FT *2 ST, RD, RT *3 MCK (NC : MSM6948V) Analog Interface Characteristics Transmit signal output (AO) Parameter Carrier Frequency Carrier Level Output Resistance Output Load Resistance Output Load Capacitance Output DC Voltage Symbol fM fS VOX ROX RLX CLX VOSX Condition SD = "1" SD = "0" RL ≥ 100 kW CL £ 40 pF — — — FT = "1" ME = "1" FT = "1" ME = "1" (VDD = 5.0 V ±5%, Ta = –25°C to 70°C) Min. 1199 1799 –2 — 100 — VDD – 0.1 2 Typ. 1200 1800 0 — — — VDD 2 Max. 1201 1801 +2 1 — 40 VDD + 0.1 2 Unit Hz dBm kW pF V fAO £ 4 kHz Note 0 dBm = 0.775 Vrms 8/13 ¡ Semiconductor Voice signal input (TI) Parameter Voltage Gain Input Signal Level Input Resistance Symbol GT VTI RTI — fTI £ 4 kHz Condition VAO/VTI FT = "1" ME = "0" Min. –2 — 50 Typ. 0 — — MSM6948/6948V Max. +2 0 — Unit dB dBm kW Built-in signal ground (SG) Parameter DC Voltage Symbol VSG Condition Without DC Load Min. VDD – 0.1 2 Typ. VDD 2 Max. VDD + 0.1 2 Unit V Receive signal input (AI) Parameter Input Resistance Receive Signal Level Bit Error Rate Symbol RIR VIR BER S/N at AI Condition fTI £ 4 kHz — 8 dB 10 dB Min. 50 –30 — — Typ. — — 1 ¥ 10–3 5 ¥ 10–5 Max. — 0 — — Unit kW dBm N/N Re-generated receive data timing clock output (RT) Parameter Data Bit Number for PLL' Lock-in Symbol NPLL1 NPLL2 CF = "1" Condition CT= "0" CT= "1" *1 Min. — — Typ. — — Max. 18 50 Unit bit *1 Data bit number to lock-in within 22.5 degree 9/13 ¡ Semiconductor MSM6948/6948V BUILT-IN FILTER FREQUENCY CHARACTERISTICS GAIN (dB) 1 0 –10 –20 –30 –40 –50 –60 Transmit Low-Pass Filter –70 2 3 4 5 6 7 8 FREQ (kHz) 9 10 GAIN (dB) 0.5 0 –10 –20 –30 –40 –50 –60 Receive Band-Pass Filter –70 1 1.5 2 2.5 3 3.5 FREQ (kHz) 4 10/13 ¡ Semiconductor MSM6948/6948V APPLICATION CIRCUIT 1 Crystal 3.6864 MHz 2 3.6864 MHz Clock Transmit Control "1" : Data Signal (SD) "0" : Voice Signal (TI) Transmit Data Transmit Data Timing Clock 3 4 5 6 7 C6 VDD 9 C2 8 X1 X2 *MCK ME SD ST SG AG DG VDD 18 FT 17 CT 16 CF 15 RT 14 RD 13 AI 12 C3 AO 11 C4 TI 10 C5 + – +5 V C1 Filter Test PLL's Lock-in Speed "1" : Low Speed "0" : High Speed Phase Correcting Speed "1" : High Speed Correction "0" : Low Speed Correction Receive Data Timing Clock Receive Data Receive Analog Signal Transmit Analog Signal Voice Signal *NC : MSM6948V 11/13 ¡ Semiconductor MSM6948/6948V PACKAGE DIMENSIONS (Unit : mm) DIP18-P-300-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. 12/13 ¡ Semiconductor MSM6948/6948V (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/13