MSM6998

E2U0010-28-81 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 ¡ Semiconductor Single Chip CODEC This version: Aug. 1998 MSM6996H/6996V/6997H/6997V/6998/6999 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 are a single-channel CODEC CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from 300 Hz to 3400 Hz. FEATURES • Compliance with ITU-T companding Law MSM6996H/MSM6996V/MSM6998 : A-law MSM6997H/MSM6997V/MSM6999 : m-law • Capable of independent operation of transmission and reception • Transmission clock in the range of 64 kHz to 2048 kHz • Adjustable transmit gain • 600 W drive for analog output MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive MSM6998/MSM6999 Push-pull drive • Built-in analog loop back fanction MSM6996V/MSM6997V • Built-in reference voltage source • Low Power Dissipation (60 mW to 70 mW Typ.) • Package options : 16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM6996HRS/MSM6997HRS) (Product name : MSM6996VRS/MSM6997VRS) (Product name : MSM6998RS/MSM6999RS) 16-pin cer DIP (DIP16-G-300-2.54-1) (Product name : MSM6996HAS/MSM6997HAS) (Product name : MSM6996VAS/MSM6997VAS) (Product name : MSM6998AS/MSM6999AS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K) (Product name : MSM6996VGS-K/MSM6997VGS-K) (Product name : MSM6998GS-K/MSM6999GS-K) 1/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 BLOCK DIAGRAM MSM6996H/V MSM6997H/V AIN+ AIN– GSX VDD VSS AG DG *2 TMC + – SAMPLE Pre Filter 5th LPF 3rd HPF Auto Zero Voltage REF. COMP Transmit PLL XSYNC C Ladder SAR Transmit Controller XCLOCK PCMOUT *1 PDN/BS PCMIN RCLOCK RSYNC T.PWD R.PWD C Ladder – + Receive Controller Receive PLL AOUT 5th LPF * 1 BS : Only MSM6997H/V * 2 Only MSM6996V, MSM6997V MSM6998, MSM6999 AIN+ AIN– GSX VDD VSS AG DG AOUT– + – + – SAMPLE 5th LPF 3rd HPF Auto Zero Pre Filter COMP Transmit PLL XSYNC Voltage REF. C Ladder SAR Transmit Controller XCLOCK PCMOUT *3 PDN/BS PCMIN RCLOCK RSYNC T.PWD R.PWD R 5th LPF C Ladder R AOUT+ – + Receive Controller Receive PLL *3 BS : Only MSM6999 2/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 PIN CONFIGURATION (TOP VIEW) AIN+ 1 AIN– 2 GSX 3 AG 4 AOUT 5 NC 6 VDD 7 PCMIN 8 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK AIN+ 1 AIN– 2 GSX 3 AG 4 AOUT 5 TMC 6 VDD 7 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK AIN+ 1 AIN– 2 GSX 3 AG 4 AOUT+ 5 AOUT– 6 VDD 7 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK 9 RCLOCK 9 RCLOCK PCMIN 8 9 RCLOCK PCMIN 8 NC : No connect pin 16-Pin Plastic DIP MSM6996HRS MSM6997HRS 16-Pin Plastic DIP MSM6996VRS MSM6997VRS 16-Pin Plastic DIP MSM6998RS MSM6999RS AIN+ 1 AIN– 2 GSX 3 AG 4 AOUT 5 NC 6 VDD 7 PCMIN 8 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK AIN+ 1 AIN– 2 GSX 3 AG 4 AOUT 5 TMC 6 VDD 7 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK AIN+ 1 AIN– 2 GSX 3 AG 4 AOUT+ 5 AOUT– 6 VDD 7 16 VSS 15 PCMOUT 14 PDN/BS 13 DG 12 XSYNC 11 RSYNC 10 XCLOCK 9 RCLOCK 9 RCLOCK PCMIN 8 9 RCLOCK PCMIN 8 NC : No connect pin 16-Pin Cer DIP MSM6996HAS MSM6997HAS 16-Pin Cer DIP MSM6996VAS MSM6997VAS 16-Pin Cer DIP MSM6998AS MSM6999AS 3/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 AIN+ 1 AIN– 2 GSX 3 AG 4 AG 5 NC 6 NC 7 AOUT 8 NC 9 NC 10 VDD 11 PCMIN 12 24 VSS 23 PCMOUT 22 PDN/BS 21 DG 20 NC 19 NC 18 NC 17 NC 16 XSYNC 15 RSYNC 14 XCLOCK 13 RCLOCK AIN+ 1 AIN– 2 GSX 3 AG 4 AG 5 NC 6 NC 7 AOUT 8 NC 9 TMC 10 VDD 11 PCMIN 12 24 VSS 23 PCMOUT 22 PDN/BS 21 DG 20 NC 19 NC 18 NC 17 NC 16 XSYNC 15 RSYNC 14 XCLOCK 13 RCLOCK NC : No connect pin 24-Pin Plastic SOP MSM6996HGS-K MSM6997HGS-K NC : No connect pin 24-Pin Plastic SOP MSM6996VGS-K MSM6997VGS-K AIN+ 1 AIN– 2 GSX 3 AG 4 AG 5 NC 6 NC 7 AOUT+ 8 NC 9 AOUT– 10 VDD 11 PCMIN 12 24 VSS 23 PCMOUT 22 PDN/BS 21 DG 20 NC 19 NC 18 NC 17 NC 16 XSYNC 15 RSYNC 14 XCLOCK 13 RCLOCK NC : No connect pin 24-Pin Plastic SOP MSM6998GS-K MSM6999GS-K 4/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX These three pins are used for the transmit level adjustment. AIN+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit amplifier. AIN– is an inverting analog input pin which is connected to the inverting input of the transmit amplifier. GSX is a transmit amplifier output pin. Adjustment can be done by following method. Analog Input C1 R1 R2 AIN+ + AIN– GSX – RC Active Filter R3 AG Gain = 1 + R2 R3 < 10 Notes: 1. R2 + R3 > 10 kW 2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should provide for DC blocking. In this case, cut-off frequency of HPF, composed by R1 and C1, should be less than 30 Hz. 3. R1 should be less than 20 kW AG AG is an analog ground. AG is connected to the analog system ground. AOUT AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V. The output voltage range is 5 VPP. This output can drive the 600 W resistor. AOUT+, AOUT– Analog output for the MSM6998 and MSM6999. The output signal amplitudes are 5 VPP. The AOUT– output is inverted to the AOUT+ output. These outputs can drive a 600 W impedance. VDD VDD is the positive power supply. The voltage supplied to this pin should be +5 V ± 5%. 5/21 ¡ Semiconductor PCMIN MSM6996H/6996V/6997H/6997V/6998/6999 PCM signal input. The serial input PCM signal is converted from digital to analog, synchronizing with the synchronous signal RSYNC and clock signal RCLOCK. The data rate of PCM signal ranges from 64 kbps to 2048 kbps. The PCM signal is read at the falling edge of the clock signal and latched into the internal register when finished to read eight bits data. The top of the PCM data is specified by RSYNC pulse timing. RCLOCK Receive clock pulse input. The frequency of this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin. This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more. In the case of a burst clock, input the following timing. PCMIN MSD 1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 RCLOCK RSYNC 9 Clocks are required XCLOCK Transmit clock input. The PCM output data rate from the PCMOUT pin is set by this clock frequency. The applicable clock frequencies range from 64 kHz to 2048 kHz. This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more. In the case of a burst clock, input the following timing. PCMOUT MSD 1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 XCLOCK XSYNC 9 Clocks are required 6/21 ¡ Semiconductor RSYNC MSM6996H/6996V/6997H/6997V/6998/6999 Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. The whole timing signal in the receive section are synchronize by this synchronizing signal. This signal must be synchronize in phase with RCLOCK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics of receive section. However, same as the RCLOCK frequency, this device can operate in the range of 8 kHz ± 2 kHz, with no guarantee of adherence to the electrical characteristics in this specification as a catalogue value. Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. All transmit timing signals are triggered to synchronize with this signal. This signal should be synchronized in phase with XCLOCK pulse. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics of transmit section. Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state. DG Ground of digital signal. This pin is electrically separated from the AG pin in this device. The DG pin must be connected to the AG pin on the printed circuit board to make common to the AG pin. PDN/BS Power down signal input. When this input is held at low level more than 1 ms, the device is put into the power-down mode. PCMOUT PCM signal output. The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse, according to the timing of XSYNC and XCLOCK pulse.). During the PCMOUT signal output except the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily possible at this pin. The code companding law and output code format depend on ITU-T Recommendation G.711, and for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by inverting the even bits of signals. Input/Output Level +Full scale +0 –0 –Full scale 1 1 0 0 0 1 1 0 PCMIN/PCMOUT MSM6996 (A-law) MSM6998 (A-law) 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 MSM6997 (m-law) MSM6999 (m-law) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 7/21 ¡ Semiconductor TMC MSM6996H/6996V/6997H/6997V/6998/6999 Control signal input for mode selection. This pin select the normal operating mode or analog loop-back mode. TMC Input > 2.0 V < 0.8 V Mode Normal operation Analog loop-back AIN + – TRANSMIT BPF AD PCMOUT AOUT + – AG RECV LPF DA PCMIN Signal flow in normal operating mode Signal flow in analog loop-back mode VSS Negative voltage power supply. The range of power supply voltage is –5 V ± 5%. 8/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VSS VAIN VDIN TSTG Condition — — — — — Rating 0 to 7 –7 to 0 VDD –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Analog Input Voltage Input High Voltage Input Low Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Timing Receive Sync Timing Transmit Sync Pulse Width Receive Sync Pulse Width PCMIN Set-up Time PCMIN Hold Time BS Set-up Time * BS Hold Time * Analog Output Load Symbol VDD VSS Ta VAIN VIH VIL fC fS DL tIr tIf tXS tSX tRS tSR tWX tWR tDS tDH tBS tBH RAL CAL Digital Output Load Allowable Analog Input Offset Voltage RDL CDL VIO Condition — — — Connect AIN– and GSX XSYNC, XCLOCK, PCMIN, RSYNC, RCLOCK, TMC, PDN/BS XCLOCK, RCLOCK XSYNC, RSYNC XCLOCK, RCLOCK XSYNC, XCLOCK, PCMIN, RSYNC, RCLOCK (Fig. 1) XCLOCKÆXSYNC (Fig. 2) XSYNCÆXCLOCK (Fig. 2) RCLOCKÆRSYNC (Fig. 2) RSYNCÆRCLOCK (Fig. 2) — — — — — — AOUT, AOUT+, AOUT– GSK — — Transmit gain stage, Gain = 1 Transmit gain stage, Gain = 10 Min. 4.75 –5.25 0 — 2.0 0 64 — 40 — — 50 100 50 100 1/fc 1/fc 100 100 200 200 600 10 — 1 — –200 –20 Typ. 5 –5 25 — — — — 8 50 — — — — — — — — — — — — — — — — — — — (Ta = 0°C to 70°C) Max. 5.25 –4.75 70 5 VDD 0.8 2048 — 60 50 50 — — — — — — — — — — — — 100 — 100 +200 +20 Unit V V °C VP-P V V kHz kHz % ns ns ns ns ns ns ms ms ns ns ns ns W kW pF kW pF mV * : The value for the MSM6997 and MSM6999 9/21 ¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70˚C) Parameter Power Supply Current (Operating) Power Supply Current (Stand-by) Input High Voltage Input Low Voltage Input Leakage Current Output Low Voltage Output Leakage Current Analog Output Offset Voltage Input Capacitance Analog Input Resistance Symbol IDD1 ISS1 IDD2 ISS2 VIH VIL IIH IIL VOL IOH VOFF CIN RIN — fIN < 3.4 kHz — Condition XCLOCK, RCLOCK 2048 kHz * * Min. — — — — 2.2 — — — — — –150 — — Typ. 7.0 6.5 — — — — < 0.5 < 0.2 0.1