MSM7502

E2U0023-28-81 ¡ Semiconductor MSM7502 ¡ Semiconductor Multi-Function PCM CODEC This version: Aug. 1998 MSM7502 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM7502, developed especially for low-power and multi-function applications in touchtone telephone sets and digital telephone terminals of digital PBXs, is a single +5 V power supply CODEC device. The device consists of the analog speech paths directly connectable to a handset, the calling circuit directly connectable to a piezosounder, the push-button key scanning interface between push buttons and control processors, the dial tone generator, the m-law/A-law CODEC, and the processor interface. The functions can be controlled via 8-bit data bus. For the CODEC of the MSM7502, an MSM7543 is used as a core CODEC, so the MSM7502 provides the available bit clock range wider than the family product MSM6895. In addition, the MSM7502 performs the greater key interface function and offers the upgraded side-tone level, receive level, and speaker pre-amplifier output level. FEATURES • Single +5 V Power Supply • Low Power Dissipation Power ON Mode : 30 mW Typ. 53 mW Max. Power Saving Mode : 2 mW Typ. 5 mW Max. • In compliance with ITU-T’s companding law • Transmission clocks : 64, 128, 256, 512, 1024, 2048 kHz 96, 192, 384, 768, 1536, 1544 kHz • Built-in PLL • Built-in Reference Voltage Supply • Calling Tone Interval : Controlled by processor • Calling Tone Combination : Controlled by processor, 6 modes • Calling Tone Volume : Controlled by processor, 4 modes • Ringing Tone Interval : Controlled by processor • Ringing Tone Frequency : Controlled by processor, 6 modes • Ringing Tone Level : Controlled by processor, 4 levels • Built-in PB Tone Generator • Built-in Speech path Control Switches • General Latch Output for External Control : 2 bits • Watch-dog Timer : 500 ms • Key Scanning I/O Output : 8 bits Input : 8 bits • Direct Connection to Handset : 1.2 kW driving available • Built-in Pre-amplifier for Loud-speaker • Hand-free Interface • m-law/A-law Switchable CODEC • LCD Deflection Angle Voltage : Controlled by processor, 8 levels • Package : 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7502GS-BK) 1/35 ¡ Semiconductor MSM7502 BLOCK DIAGRAM TPAO TPBI MPAI MPAO MPBI MPBO MLDYI TO CAI 20 dB TPAI + VOL 9 – AIN SW 2 SW 7 VOL 8 + SW 16 VOL 4 AOUT VOL 10 – PLL BCLOCK XSYNC RSYNC WRN RDN CEN RESETN D0 to D7 AD0 AD1 INTT TIMEN PCMIN 5.7 dB VOL 3 m/A CODEC SW 12 PCMOUT + – SW 1 0 dB CAO R1I VOL 1 R2I SW 9 0 dB VOL 2 –8.7 dB 0 dB RPO RMI RMO0 RMO1 0 dB – SW 5 – – VOL 7 SW 3 SW 4 SW 17 SW 14 SW 13 R-TONE GEN. 400 425 440 450 400*16 400*20 PB GEN. SW 5 F-TONE GEN. 1 kHz SPI SW 10 VOL 6 0 dB –3 dB SW 6 SW 8 SW 18 S-TONE GEN. WAMBLE TONE 1000 Hz 800 Hz 400 Hz Latch – –6.8 dB VOL 5 –22 dB SPO – VOL 11 VOL 12 SW 21 SW 15 SW 11 VLCD GEN. SW 20 PROCESSOR INTF LA LB LML VLCD SA0 VOL 13 SA1 SW 19 KEY INTF SCANNING OUTPUT SCANNING INPUT SG GEN. VA VD AG DG SGT SGC PO0 to PO7 PI0 to PI7 2/35 ¡ Semiconductor MSM7502 PIN CONFIGURATION (TOP VIEW) 78 RESETN 79 TIMEN 75 WRN 80 INTT 77 CEN 76 RDN 74 AD1 73 AD0 72 DB7 71 DB6 70 DB5 69 DB4 68 DB3 67 DB2 66 DB1 65 DB0 64 VD 63 PI7 62 PI6 61 PI5 60 PI4 59 PI3 58 PI2 57 PI1 56 PI0 55 NC 54 PO0 53 PO1 52 PO2 51 PO3 50 PO4 49 PO5 48 PO6 47 PO7 46 PCMOUT 45 BCLOCK 44 XSYNC 43 RSYNC 42 PCMIN 41 NC LML 1 LA 2 LB 3 VLCD 4 SA1 5 SA0 6 DG 7 AG 8 RMO1 9 RMO0 10 RMI 11 SPI 12 NC 13 SPO 14 RPO 15 R2I 16 R1I 17 MLDYI 18 MPBO 19 MPBI 20 MPAO 21 NC 22 MPAI 23 NC 24 TPBI 26 TPAO 27 SGC 36 TPAI 29 NC : No connect pin 80-Pin Plastic QFP CAO 39 SGT 30 CAI 34 NC 40 NC 25 NC 35 NC 38 NC 28 TO 31 NC 33 NC 37 VA 32 3/35 ¡ Semiconductor MSM7502 PIN AND FUNCTIONAL DESCRIPTIONS LA, LB General latch outputs for external control. Statuses of these outputs are controlled via the processor interface. Refer to the description of the control data for details. These outputs provide the capability to drive one TTL. DG Digital Ground. DG is separated from the analog ground AG inside the device. But, DG should be connected as close to the AG pin on PCB as possible. AG Analog Ground. SA0, SA1 Sounder (calling tone) driving outputs. The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily configured by connecting a piezo-sounder between SA0 and SA1. Through processor control, the calling tone volume is selectable from four levels and one of six tone combinations is selectable. Initially, the ringing tone volume is set at a maximum and the tone combination is set at a 16 Hz Wamble tone by a combination of 1 kHz and 1.3 kHz. If these pins are used with no-load, tone volume cannot be controlled. When tone volume control is required, a load resistor must be connected between SA0 and SA1. 4/35 ¡ Semiconductor RMI, RMO0, RMO1 MSM7502 Receive main amplifier input and outputs. RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier. The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a handset is directly connected between RMO0 and RMO1. During the system power down, the RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is determined by a resistor connected between RPO and RMI, and a resistor connected between RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezoreceiver with an impedance greater than 1.2 kW is available. If the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech path is provided by processor control. A circuit example for adjustment of frequency characteristics RPO RMI RMO0 R1 C1 R2 C2 Main amplifier gain without capacitors G= R2 R1 5/35 ¡ Semiconductor SPI MSM7502 Addit0ion input of speaker amplifier. The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a gain between 0 dB and –18 dB in a 6 dB step, or a gain between 0 dB and –28 dB in a 4 dB step through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by gain setting). SPO Output of pre-amplifier for speaker. Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker. During the whole system power down mode, SPO is at an analog ground level. During the whole system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone, F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from the speaker by processor control. When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the CAO pin for CODEC output is internally connected. R1I, R2I, RPO R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier. Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO), and R2I is used as the mixing signal input pin. The typical gain between R1I and PRO is –6 dB. Through processor control, gains are variable from –14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of –9, –6, –3, or 0 dB. The gain between R2I and RPO is fixed to 0 dB. During the whole system power-on mode, the RPO output is in non-signal state, and speech signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control. During the whole system power-down mode, the RPO output is the analog ground level. The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The input resistance of R2I is typically 20 kW. MLDYI Hold tone signal input. For example, the output of external melody IC is connected to this pin. Through processor control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The typical gain between MLDYI and TO is –2 dB. Through processor control, a gain between –2 dB and –11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is –3 dB. Through processor control, a gain between –3 dB to –31 dB is also settable at 4 dB steps. MLDYI is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT. 6/35 ¡ Semiconductor TPBI, TO MSM7502 TPBI is the input and TO is the output of the transmit pre-amplifier (B). When the handset is used, TPBI is connected to the transmit pre-amplifier (A) output pin (TPAO). If adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between TPAO and TPBI. Through processor control, the signal applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin. During the whole system power down mode, TO is at an analog ground level. The typical gain between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7 dB is also settable at 3 dB steps. The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between –9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW resistor between TPBI and SGT. A circuit example for adjustment of frequency characteristics TPAO TPBI SGT R3 C4 C3 R4 MPAI, MPAO Handfree microphone pre-amplifier (A) input and output. MPAI is the input and MPAO is the output. The speech path between MPAI and MPAO is always active regardless of processor control. During the whole system power saving mode, MPAO is at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance input, so insert an about 100 kW between MPAI and SGT. MPBI, MPBO The handfree microphone (B) input and output. MPBI is the inverted input and MPBO is the output. With an external resistance, the amplifier gain is adjusted in the range between –25 dB and +25 dB. A signal on the MPBO is output via the TO pin through processor control. During the whole system power down mode, MPBO is at an analog ground level. The gain between MPBO and TO is fixed to 0 dB. 7/35 ¡ Semiconductor TPAI, TPAO MSM7502 The transmit pre-amplifier input and output. TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from SGT). The transmit path from TPAI to TPAO is always active regardless of processor control. During the whole system power down mode, TPAO is at an analog ground level. The gain between TPAI and TPAO is fixed to 20 dB. SGT Transmit path signal ground. SGT outputs half the supply voltage. During the whole power down mode, SGT is in a high impedance state. SGC Bypass capacitor connecting pin for signal ground level. Insert a 0.1 mF high performance capacitor between SGC and AG. VA, VD +5 V power supply. VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V analog path of the system. CAI, CAO CODEC analog input and output. CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an about 100 kW bias resistor between CAI and SGT. CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling capacitor. A bias resistor is not required to R1I. During the whole system or CODEC power down mode, CAO is at the SG voltage level. 8/35 ¡ Semiconductor BCLOCK MSM7502 CODEC PCM data I/O shift clock input. The frequency is one of 64 kHz, 128 kHz, 256 kHz, 512 kHz, 1024 kHz, 2048 kHz, 96 kHz, 192 kHz, 384 kHz, 786 kHz, 1536 kHz, and 1544 kHz. If the BCLOCK signal is not applied, PLL is out of synchronization and the CODEC path goes into the power down mode. XSYNC, RSYNC Synchronous signal input. CODEC PCM data is sent out sequencially via the PCMOUT pin from MSB at the rising edge of the BCLOCK signal in synchronization with the rise of the XSYNC signal. PCM data should be entered via the PCMIN pin with MSB at the head in synchronization with the rise of the RSYNC signal. PCM data is shifted in at the falling edge of the BCLOCK signal. Since the XSYNC signal is used for a trigger signal for PLL and for a clock signal to the tone generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out of synchronization and the CODEC path goes into a power down mode. This signal has to be synchronous with the BCLOCK signal and its frequency must be within 8 kHz ± 50 ppm to ensure the CODEC AC characteristics (mainly frequency characteristics). PCMIN PCM signal input. PCMIN data is shifted in at the falling edge of the BCLOCK signal and is latched into the internal register after eight bits are shifted. PCMOUT PCM signal output. PCMOUT data is shifted out at the rising edge of the BCLOCK signal. PCMOUT is left open after eight bits are shifted or when PLL goes out of synchronization. PCMOUT also is left open through processor control. In addition, a digital path between PCMIN and PCMOUT is formed through processor control. PCMOUT needs a pull-up resistor because of its open-drain circuit. 9/35 ¡ Semiconductor PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7 MSM7502 Key scanning outputs. These output pins need external pull-up resistors because of their open- drain circuits. But, when these are used in combination with PI0 to PI7, pull-up resistors are not required. Through processor control, these outputs can be set open or to digital "0". Initially, these outputs are set at an opened state. PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7 Key scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7). Since these inputs are pulled up inside the IC, external resistors are not required. INTT Interrupt signal output to the processor. INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control signal from the processor. This output keeps digital "0" unless the interrupt is released. INTT does not output any signal while no XSYNC signal is input. When the RESETN signal is in "0" state, INTT is in "1" state. INTT goes from "1" state to "0" state 8 ms after the RESETN signal goes to "1" state. Interrupt release signal from processor t < 8 ms 8 ms < t < 16 ms t < 8 ms INTT output 8 ms 16 ms 8 ms DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7 Data bus inputs and outputs. These pins are configured as an output during the READ mode only and as an input during other modes. 10/35 ¡ Semiconductor AD0, AD1 MSM7502 Address data inputs for the internal control registers. Addressing of the internal control registers is executed by AD0 and AD1 and sub address data, DB7 and DB6. AD1 AD0 DB7 DB6 0 0 0 0 1 1 0 WRITE 0 1 0 1 1 1 1 1 1 1 READ 1 0 1 1 1 1 0 — 0 0 1 1 — 0 1 0 1 0 1 0 1 — 0 1 0 1 — Function ON/OFF controls of sounder, R-Tone, F-Tone Level/Frequency controls of sounder, R-Tone PB tone control Controls of internal speech path switch and general latch Watchdog timer reset Controls of receive gain and side tone gain Controls of transmit hold tone, PB tone, handfree input, handset inputs gain Controls of speaker pre-amplifier gain and additional speaker gain Controls of receive PAD and incoming tone input gain Key scanning output control Key scanning interrupt reset LCD deflection angle control voltage setting Power ON/OFF control CODEC control (Controls of companding law and digital loop) Key scanning data read-out WRN Write signal for internal control registers. Data on the data bus is written into the registers at the rising edge of WRN under the condition of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals. RDN Read signal input to read PI0 to PI7 out of the processor. When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid. 11/35 ¡ Semiconductor CEN Chip Enable signal input. When CEN is in digital "0" state, WRN and RDN are valid. MSM7502 RESETN Reset signal input. Digital "0" input to RESETN makes all of internal control registers to be initialized. When powered on, this RESETN signal should be input for initializing the system. TIMEN Watchdog timer output. When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal is continuously output. When RESETN is at digital "0", this timer is reset. And, in about 500 ms after RESETN goes to digital "1", the first timer output signal is issued and then the timer signal is output at intervals of a 500 ms. If the SYNC signal is not input, the TIMEN signal is not output. LML Control signal output for external hold tone generator. LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0" state. VLCD By processor control, VLCD outputs a DC voltage between 0 and 1.7 V is about 0.25 V step. This is used to control the deflection angle of the LCD display. VLCD has the internal resistance value of about 1 kW, so the external load of over 100 kW should be used. During initialized state, VLCD outputs the voltage of 0 V. 12/35 ¡ Semiconductor MSM7502 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition AG, DG = 0 V AG, DG = 0 V AG, DG = 0 V — Rating 0 to 7 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 Unit V V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Symbol VD Ta VIH VIL tIr tIf RDL Digital Output Load CDL Condition VA, VD (Voltage must be fixed) — All Digital Input Pins All Digital Input Pins All Digital Input Pins All Digital Input Pins PO0 to PO7 PCMOUT PO0 to PO7 PCMOUT Min. 4.75 –10 2.2 0 — — 10 0.5 — Typ. 5.0 +25 — — — — — — — Max. 5.25 +70 VDD 0.8 50 50 — — 100 Unit V °C V V ns ns kW pF Recommend Operating Conditions (Analog Interface) Parameter Symbol Condition TPAO, MPAO, MPBO, TO, Analog Load Resistance RAL RPO, SPO, CAO RMO0, RMO1 with respected to SG Level Analog Load Capacitance CAL TPAO, MPAO, MPBO, TO, RPO, SPO, CAO RMO0, RMO1 TPAI, TPBI, MPAI Allowable Analog Input Offset Voltage Voff MLDY R1I, R2I, SPI CAI Min. 20 0.6 — — –10 –50 –25 –100 Typ. — — — — — — — — Max. — kW — 100 70 +10 +50 +25 +100 mV pF nF Unit 13/35 ¡ Semiconductor Recommended Operating Conditions (CODEC Digital Interface) Parameter Symbol Condition BCLOCK XSYNC, RSYNC BCLOCK BCLOCKÆX, RSYNC See Fig.1 X, RSYNCÆBCLOCK See Fig.1 XSYNC, RSYNC PCMIN PCMIN XSYNC, RSYNC Min. Typ. MSM7502 Max. Unit Clock Frequency Sync Pulse Frequency Clock Duty Ratio FC FS DC tXS 64, 128, 256, 512, 1024, 2048 96, 192, 384, 768, 1536, 1544 6.0 40 — — 1 BCK 100 100 — 8.0 50 — — — — — — 10.0 60 100 100 100 — — 500 kHz kHz % ns ns ms ns ns ns Sync Pulse Setting Time tSX Sync Pulse Width Data Setup Time Data Hold Time Allowable Jitter Width tWS tDS tDH — Recommended Operating Conditions (Processor Digital Interface) Parameter Write Pulse Period Write Pulse Width Read Pulse Width Address Data Setup Time Address Data Hold Time CEN Setup Time CEN Hold Time Data Setup Time Data Hold Time Reset Pulse Width Symbol PW TW TR tAW1 tAR1 tAW2 tAR2 tCW1 tCR1 tCW2 tCR2 tDW1 tDW2 tWRES Condition WRN WRN RDN AD0, AD1ÆWRN AD0, AD1ÆRDN WRNÆAD0, AD1 RDNÆAD0, AD1 CENÆWRN CENÆRDN WRNÆCEN RDNÆCEN DB0 to 7ÆWRN WRNÆDB0 to 7 RESETN See Fig.2 Min. 2000 100 200 10 80 50 10 10 80 50 10 110 20 110 Typ. — — — — — — — — — — — — — — Max. — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14/35 ¡ Semiconductor MSM7502 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Power Supply Current Input High Voltage Input Low Voltage High Input Leakage Current Low Input Leakage Current Digital Output High Voltage Digital Output Low Voltage Digital Output Leakage Current Analog Output Offset Voltage Input Capacitance Symbol IDD1 IDD2 IDD3 VIH VIL IIH IIL VOH VOL IO Voff CIN Condition Operating Mode (No Signal, Sounder OFF) Whole system Power Down CODEC Power Down — — Digital Pins except for PI0 to PI7 PI0 to PI7 (Internal Pull-up Pins) Digital Pins except for PI0 to PI7 PI0 to PI7 (Internal Pull-up Pins) IOH = 0.4 mA IOH = 1 mA IOL = –1.6 mA PCMOUT, DB0 to DB7 (Write Mode) TPAO, MPAO, MPBO, TO, CAO, RPO, RMO0, RMO1, SPO — TPAI, TPBI, MLDYI, RMI, MPAI, MPBI R1I, R2I, SPI CAI (fin : < 4 kHz) SG Voltage SG Drive Current Equivalent Pull-up Resistance — ISGF ISGS RPULL — FORCE Current SINK Current PI0 to PI7, VI = 0 V Min. — — — 2.2 0.0 — — — 10 2.4 3.8 0.0 — –100 — — 10 — VA/2 –0.05 1.0 0.3 200 Typ. 6.0 0.4 2.8 — — — — — — — — — — — 5 10 — 1 VA/2 1.5 0.5 370 Max. 10.0 0.8 5.0 VDD 0.8 2.0 2.0 0.5 25 VDD VDD 0.4 10 +100 — — — — VA/2 +0.05 — — 500 Unit mA mA mA V V mA mA mA mA V V mA mV pF MW kW MW V mA kW Analog Input Resistance RIN 15/35 ¡ Semiconductor AC Characteristics 1 (CODEC) MSM7502 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Freq. Level (Hz) (dBm0) Loss T1 60 Loss T2 300 Loss T3 1020 0 Loss T4 2020 Loss T5 3000 Loss T6 3400 Loss R1 300 Loss R2 1020 0 Loss R3 2020 Loss R4 3000 Loss R5 3400 SD T1 3 SD T2 0 SD T3 1020 –30 SD T4 –40 SD T5 –45 SD R1 3 SD R2 0 SD R3 1020 –30 –40 SD R4 –45 SD R5 GT T1 3 GT T2 –10 GT T3 1020 –40 GT T4 –50 GT T5 –55 GT R1 3 GT R2 –10 GT R3 1020 –40 GT R4 –50 GT R5 –55 Condition Min. 20 –0.20 –0.15 –0.15 0.0 –0.15 –0.15 –0.15 0.0 35 35 35 29 24 37 37 37 30 25 –0.2 –0.2 –0.4 –1.2 –0.2 –0.2 –0.5 –1.2 Typ. 27 +0.07 Reference –0.03 +0.06 0.38 –0.03 Reference –0.02 +0.15 0.56 43.0 41.0 38.0 31.0 26.5 43.0 41.0 40.0 34.0 31.0 +0.01 Reference –0.05 +0.05 +0.30 0.0 Reference –0.10 –0.30 –0.40 Max. — +0.20 +0.20 +0.20 0.80 +0.20 +0.20 +0.20 0.80 — — — — — — — — — — +0.2 +0.2 +0.4 +1.2 +0.2 +0.2 +0.5 +1.2 dB Unit Transmit Frequency Response Receive Frequency Response dB Transmit Signal to Distortion Ratio *1 dB Receive Signal to Distortion Ratio *1 dB Transmit Gain Tracking dB Receive Gain Tracking dB Note: *1 Psophometric filter is used 16/35 ¡ Semiconductor AC Characteristics 1 (CODEC) (Continued) MSM7502 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Freq. Level (Hz) (dBm0) Nidle T Idle Channel Noise Nidle R Absolute Amplitude Absolute Delay Time AV T AV R Td tgd T1 tgd T2 tgd T3 tgd T4 tgd T5 tgd R1 tgd R2 tgd R3 tgd R4 tgd R5 CR T CR R DIS S IMD PSR T PSR R — 1020 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 1020 4.6 kHz to 72 kHz Condition AIN = SG *1 *1 *3 *2 Min. — — 0.5671 0.5671 Typ. –73.5 –71 –78.0 0.6007 0.6007 0.58 0.19 0.12 0.02 0.05 0.08 0.0 0.0 0.0 0.09 0.12 78 86 32.0 –37.5 –52 30 Max. –70 –69 Unit — — — 0 0 dBmOp –75 0.6363 0.6363 0.60 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 — — — –35 –35 — Vrms ms A to A BCLOCK = 64 kHz — — — — — — — — — — — 70 75 30 — — — Transmit Group Delay 0 *4 ms Receive Group Delay 0 *4 ms Crosstalk Attenuation Discrimination Out-of-band Signal Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio 0 –25 0 –4 50 mVpp Transmit Æ Receive Receive Æ Transmit 0 to 4000 Hz 4.6 kHz to 100 kHz 2fa–fb *5 dB dB dBmO dBmO dB 300 to 3400 fa = 470 fb = 320 0 to 50 kHz Notes: *2 *3 *4 *5 Upper is specified for the m-law, lower of the A-law PCMIN input : idle CODE Minimum value of the group delay distortion The measurement under idle channel noise 17/35 ¡ Semiconductor AC Characteristics 2 (Transmit Path) MSM7502 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Pre-Amp Gain Transmit Path Gain Transmit Path Gain Setting (VOL8) Microphone Pre-Amp Gain Microphone Pre-Amp Gain Setting (VOL9) Additional Transmit Signal Gain In-Channel PB Signal Output Level In-Channel PB Signal Output Level Setting (VOL4) In-Channel PB Signal Frequency Deviation In-Channel PB Signal Distortion Hold Tone Path Gain Hold Tone Path Gain Setting (VOL3) Symbol Freq. (Hz) GTPA GTPB1 1020 RG1TPB RG2TPB RG3TPB GMPA RG1MPA RG2MPA GTMX VPBT1 GPBT1 GPBT2 GPBT3 DfPBT THDPBT GPAT RG1PAT RG2PAT RG3PAT 1020 –4.0 1020 — –4.0 — 1020 –24.0 –24.0 Level (dBV) Condition TPAI-TPAO TPBI-TO Set at typical gain For –3 dB typical –6 dB setting –9 dB MPAI-MPAO Set at typical gain For typical setting –6 dB –9 dB Min. 18.0 15.7 –5.0 –8.0 –11.0 18.0 –8.0 –11.0 –2.0 –19.4 –5.0 –8.0 –11.0 –1.0 In-band Distortion MLDYI-TO Set at typical gain For –3 dB typical –6 dB setting –9 dB TPAI:Terminated in 510 W Measured at TO TPAO-TPBI Directly connected Set at typical gain *6 TPAO, TO, MPAO, MPBO RL = 20 kW — –4.0 –5.0 –8.0 –11.0 Typ. 20.0 17.7 –3.0 –6.0 –9.0 20.0 –6.0 –9.0 0.0 –17.4 –3.0 –6.0 –9.0 — –35 –2.0 –3.0 –6.0 –9.0 Max. 22.0 19.7 –1.0 –4.0 –7.0 22.0 –4.0 –7.0 +2.0 –15.4 –1.0 –4.0 –7.0 +1.0 –30 0.0 –1.0 –4.0 –7.0 dB Unit dB dB dB dB MPBO-TO To per wave set at typical gain For –3 dB typical –6 dB setting –9 dB dB dBV dB % dB dB dB — — — — — — Idle Channel Noise NiTPA — — — –75 — dBV Maximum Output Voltage Swing VOT 1020 — 2.4 — — VPP Note: *6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted 18/35 ¡ Semiconductor AC Characteristics 3 (Receive Main Amp.) MSM7502 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Receive Main Amp Output Gain Difference Receive Main Amp Output Phase Difference Maximum Amplitude Symbol Freq. (Hz) DGRMO DPRMO VRMO 1020 1020 1020 Level (dBV) –4.4 –4.4 — Condition RMO0/RMO1 Gain = 1 RMO0/RMO1 1.2 kW between RMO0 and RMO1. Measured at each output Min. Typ. Max. Unit — — 3.6 –0.10 –179.6 — — — — dB deg VPP AC Characteristics 3 (Receive Path) (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Freq. (Hz) GRPA RGRPA1 RGRPA2 RGRPA3 RGRPA4 RGRPA5 RGRPA6 RGRPA7 RGPAD1 RGPAD2 RGPAD3 GRMX GSIDE RGSIDE1 RGSIDE2 RGSIDE3 1020 RGSIDE4 RGSIDE5 RGSIDE6 GSP RGSP1 RGSP2 RGSP3 RGSP4 RGSP5 RGSP6 RGSP7 GSPI Level (dBV) Condition Typical gain is set between R1I and RPO –8 dB –6 dB –4 dB –2 dB 2 dB 4 dB 6 dB –3 dB –6 dB –9 dB Min. Typ. Max. Unit Receive Signal Path Gain –8.0 –10.0 –8.0 –6.0 –4.0 0.0 2.0 4.0 –5.0 –8.0 –11.0 –2.0 1.0 4.0 1.0 –5.0 –8.0 –11.0 –14.0 –2.0 –6.0 –10.0 –14.0 –18.0 –22.0 –26.0 –30.0 –2.0 –6.0 –8.0 –6.0 –4.0 –2.0 2.0 4.0 6.0 –3.0 –6.0 –9.0 0.0 3.0 6.0 3.0 –3.0 –6.0 –9.0 –12.0 0.0 –4.0 –8.0 –12.0 –16.0 –20.0 –24.0 –28.0 0.0 –4.0 –6.0 –4.0 –2.0 0.0 4.0 6.0 8.0 –1.0 –4.0 –7.0 +2.0 5.0 8.0 5.0 –1.0 –4.0 –7.0 –10.0 +2.0 –2.0 –6.0 –10.0 –14.0 –18.0 –22.0 –26.0 +2.0 dB Receive Signal Path Gain Setting (VOL1) 1020 –4.0 For typical setting dB Receive PAD Gain Setting (VOL10) Additional Receive Signal Path Gain Side Tone Path Gain For typical setting 1020 –4.0 dB R2I and RPO Typical gain is set betweenTPBI and RPO dB dB Side Tone Path Gain Setting (VOL2) Speaker Pre-Amp Gain Speaker Pre-Amp Gain Setting (VOL5) 1020 Additional Speaker Input Path Gain 1020 6 dB 3 dB For –3 dB –14.0 typical –6 dB setting –9 dB –12 dB Typical gain is set between RPO and SPO –4 dB –8 dB For –12 dB –4.0 typical –16 dB setting –20 dB –24 dB –28 dB Typical gain is set –4.0 between SPI and SPO dB dB dB dB 19/35 ¡ Semiconductor AC Characteristics 3 (Receive Path) (Continued) MSM7502 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Additional Speaker Input Path Gain Setting (VOL6) Hold Acknowledge Tone Path Gain PB Acknowledge Tone Output Level PB Acknowledge Tone Frequency Difference PB Acknowledge Tone Distortion Incoming Tone Speaker Output Path Gain Incoming Tone Speaker Output Path Gain Setting (VOL11) Symbol Freq. (Hz) RGSPI1 RGSPI2 1020 RGSPI3 GPAR VPBRP VPBSP DfPBR THDPBR GCAO RGCAO1 RGCAO2 NiRPO — — 1020 –20 — — 1020 Level (dBV) –4.0 Condition Setting, –6 dB –12 dB than typical gain –18 dB Typical gain is set RPO per wave SPO per wave Set at typical gain RPO, SPO RPO, SPO Typical gain is set between CAO and SPO Setting, –10 dB than typical gain –20 dB R1I:SG, Measured at RPO Set at typical gain. *6 R1I:SG, Measured at SPO Set at typical gain. *6 R1I:SG, Gain 0 dB RMO0, RMOB *6 RPO, SPO RL = 20 kW Min. –8.0 –14.0 –20.0 –5.0 –32.1 –30.2 –1.0 — –2.0 –12.0 –22.0 — Typ. –6.0 –12.0 –18.0 –3.0 –30.1 –28.2 — –35 0.0 –10.0 –20.0 –86.0 Max. –4.0 –10.0 –16.0 –1.0 –28.1 –26.2 +1.0 –30 +2.0 –8.0 dB –18.0 — dBV Unit dB dB dBV dBV % dB dB –4.0 between MLDYI and SPO — — — — Idle Channel Noise NiSPO — — — –89.0 — dBV NiRMO Maximum Output Amplitude VOR — — — — — 2.4 –86.0 — — — dBV VPP Note: *6. Noise band width : 0.3 kHz to 3.4 kHz, non weighted AC Characteristics 4 (Ringing Tone) (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter R-Tone Output Amplitude (VOL7) Symbol Condition Level Setting 1 Level Setting 2 RPO Level Setting 3 Level Setting 4 RPO SPO SPO Gain Setting 0 dB –10 dB –20 dB Min. 63 84 105 126 112 7.5 154 49 12 Typ. 90 120 150 180 160 11.0 220 70 17 Max. 117 156 195 234 208 14.5 286 91 22 Unit VRTO VFTRP VFTSP VSTSP mVPP F-Tone Output Amplitude S-Tone Output Amplitude (VOL12) mVPP mVPP 20/35 ¡ Semiconductor AC Characteristics 4 (Sounder Output Circuit) MSM7502 (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Freq. (Hz) VST1 VST2 VST3 VST4 Level (dBV) Condition 730 W between SA0 and SA1. Measured at each out Vol.1 Vol.2 Vol.3 Vol.4 Min. 3.25 0.73 0.25 0.13 Typ. 4.0 1.28 0.47 0.28 Max. — 1.98 0.65 0.45 Unit Sounder Tone Output Amplitude (VOL13) — — Vpp LCD Defelection Angle Control Voltage Output (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Condition DB2 DB1 DB0 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 — To GND Min. 1.40 1.25 1.05 0.85 0.65 0.35 0.15 0.0 — 100 Typ. 1.70 1.50 1.30 1.10 0.85 0.55 0.30 0.0 1.0 — Max. 2.00 1.75 1.55 1.35 1.05 0.75 0.45 0.05 — — Unit Output Voltage VLCD V Output Resistance Output Load ROLCD RLLCD kW kW Digital Interface Characteristics (VDD = 5 V ±5%, Ta = –10°C to +70°C) Parameter Digital Output (Latch) Delay Time Key Scanning Output Delay Time Digital Output (Data) Delay Time CODEC Data Output Delay Time Symbol tPDLA tPDSCN tPDDATA tPDCOD Condition WRÆLA, LB WRÆPO0 to PO7 Pull-up resistance : 10 kW RDÆDB0 to DB7 BCLOCKÆPCMOUT Pull-up resistance : 500 W Min. 0.2 0.2 20 20 Typ. — — 52 50 Max. 1.5 1.5 150 100 Unit ms ms ns ns 21/35 ¡ Semiconductor MSM7502 TIMING DIAGRAM CODEC Timing BCLOCK tSX XSYNC tWS PCMOUT MSB B2 B3 1 2 3 4 5 6 7 8 9 tXS tPDCOD B4 B5 B6 B7 B8 CODEC Transmit Timing BCLOCK tSX RSYNC tWS PCMIN MSB B2 B3 1 2 3 4 5 6 7 8 9 tXS tDS tDH B4 B5 B6 B7 B8 CODEC Receive Timing Figure 1 Processor Interface Timing AD0, AD1 tAW1 CEN tCW1 WRN TW RDN tDW1 tDW2 tPDDATA DB0 to DB7 tPDSCN PO0 to PO7 tPDLA Latch Output tPDDATA TR tCW2 tCR1 tCR2 tAW2 tAR1 tAR2 Figure 2 22/35 ¡ Semiconductor FUNCTIONAL DESCRIPTION Control Data Description Sounder and tone ON/OFF control WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data Description for Control Sounder output ON Sounder output OFF Sounder output ON Sounder output OFF R-Tone R-Tone F-Tone F-Tone F-Tone F-Tone ON OFF ON(1 kHz) OFF ON(1 kHz) OFF SW19 ON SW19 OFF SW20 ON SW20 OFF SW13 ON SW13 OFF SW14 ON, SW14 OFF, SW14 OFF, SW14 OFF, SW15 OFF, SW15 OFF, SW15 ON, SW15 OFF, Tone Output: SPO Tone Output: RPO Tone Output: SPO *1 Remarks Tone Output: SA0, SA1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 *1: This Sounder Output is sent at the timing shown below. ON OFF ON OFF 0.625 s 0.25 s 0.125 s 2s MSM7502 23/35 ¡ Semiconductor Level and frequency control of sounder and R-tone WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data Description for Control SA0, SA1 outputs sounder volume 1 (Large) SA0, SA1 outputs sounder volume 2 (Middle) SA0, SA1 outputs sounder volume 3 (Small 1) Remarks Sounder volume and tone are defind at a time. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 — — — 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 — 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 — 0 1 0 1 — 0 1 0 1 At the initial setting, sounder volume 1 and sounder SA0, SA1 outputs sounder volume 4 (Small 2) combination tone 1 are set. Sounder combination tone 1 (16 Hz wamble tone with 1000 Hz/1333 Hz) SA0, SA1 sounder volume: Sounder combination tone 2 (16 Hz wamble tone with 667 Hz/800 Hz) VOL 13 Sounder combination tone 3 (8 Hz wamble tone with 800 Hz/1000 Hz) Sounder combination tone 4 (Single tone of 1000 Hz) Sounder combination tone 5 (Single tone of 800 Hz) Sounder combination tone 6 (Single tone of 400 Hz) R-Tone output level 1 (90 mVPP at RPO output) R-Tone output level 2 (120 mVPP at RPO output) R-Tone output level 3 (150 mVPP at RPO output) R-Tone output level 4 (180 mVPP at RPO output) R-Tone 400 Hz single tone R-Tone 425 Hz single tone R-Tone 440 Hz single tone R-Tone 450 Hz single tone R-Tone 400 Hz ON/OFF by 16 Hz R-Tone 400 Hz ON/OFF by 20 Hz R-Tone output level and frequency are defined at a time. At the initial setting, output level 1 and a single 400 Hz tone are set. R-Tone output level = VOL 7 MSM7502 24/35 ¡ Semiconductor PB tone control WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X Output PB Frequency Low 697 Hz 697 Hz 697 Hz 697 Hz 770 Hz 770 Hz 770 Hz 770 Hz 852 Hz 852 Hz 852 Hz 852 Hz 941 Hz 941 Hz 941 Hz 941 Hz High 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz SW16, SW17, SW18: OFF When PBTC = 1 SW16: OFF SW17: OFF SW18: ON PB tone is sent to the receive path SPO only. When PBTC = 0 SW16: ON SW17: ON SW18: OFF PB tone is sent to the transmit path T0 and the receive path RPO. 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D Remarks DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PB 1 0 1 PBTC 0 1 1 1 1 1 1 1 1 0 0 X PB tone stop MSM7502 25/35 ¡ Semiconductor SW control and timer reset WRITE Mode Address Data AD1 = 0, AD0 = 0 Control Data Description for Control SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 LA = 1 LB = 1 ON ON ON ON ON ON ON ON ON ON ON ON Transmit handfree input Transmit handset input Receive input Side tone input Receive main amplifier input Receive speaker input Remarks When hold tone or PB tone transmit is selected, these inputs are muted. — When Handfree input is selected, side tone is muted. — DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Transmit path hold tone input When either of SW7 or SW8 is set to ON, Receive path hold tone Acknowledge input external terminal LML goes to "1". Additional receive input Additional speaker input Speaker DEC input PCM output enable General Latch output for external control — Speaker DEC input = CODEC AOUT — Above codes Above corresponding SW or latch is set to OFF or "0". All of above SWs or latches are set to OFF or "0" at the initial setting stage. Watchdog timer is reset. MSM7502 26/35 ¡ Semiconductor Gain setting (receive gain, side tone gain) WRITE Mode Address Data AD1 = 0, AD0 = 1 Control Data Description for Control Typical receive gain (–6dB) –8 dB than the typical gain –6 dB than the typical gain –4 dB than the typical gain –2 dB than the typical gain +2 dB than the typical gain +4 dB than the typical gain +6 dB than the typical gain Typical side tone gain (–9 dB) –12 dB than the typical gain –9 dB than the typical gain — –6 dB than the typical gain –3 dB than the typical gain +3 dB than the typical gain +6 dB than the typical gain Side tone OFF (VOL2 max loss) Receive gain and side tone gain are set at a time. At the initial setting, the typical gain is set. Remarks Receive gain = VOL1 Side tone gain = VOL2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 — — — 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MSM7502 27/35 ¡ Semiconductor Gain control (transmit hold tone, PB tone, microphone input, handset input) WRITE Mode Address Data AD1 = 0, AD0 = 1 Control Data Description for Control Typical transmit hold tone gain (–2 dB) –3 dB with respect to the typical gain –6 dB with respect to the typical gain –9 dB with respect to the typical gain Typical transmit PB tone gain (+4 dB) — –3 dB with respect to the typical gain –6 dB with respect to the typical gain –9 dB with respect to the typical gain 0 — 1 0 0 1 1 0 1 0 1 — — 0 1 1 0 1 0 1 Typical handfree input gain (+20 dB) –6 dB with respect to the typical gain –9 dB with respect to the typical gain — Typical handset input gain (+12 dB) –3 dB with respect to the typical gain –6 dB with respect to the typical gain –9 dB with respect to the typical gain Handfree input gain = VOL9 Handset input gain = VOL8 Handfree input gain and handset Input gain are set at a time. At the initial setting, the typical gain is set. Remarks Transmit hold tone gain = VOL3 Transmit PB tone gain = VOL4 Hold tone gain and PB tone gain are set at a time. At the initial setting, the typical gain is set. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 — 0 0 0 1 0 1 0 1 0 1 0 1 — 0 1 1 0 1 0 1 MSM7502 28/35 ¡ Semiconductor Gain control (receive PAD, speaker) WRITE Mode Address Data AD1 = 0, AD0 = 1 Control Data Description for Control Typical speaker amp. gain (0 dB) -4 dB with respect to the typical gain -8 dB with respect to the typical gain -12 dB with respect to the typical gain -16 dB with respect to the typical gain -20 dB with respect to the typical gain -24 dB with respect to the typical gain -28 dB with respect to the typical gain Typical additional speaker input path gain (0 dB) — -6 dB with respect to the typical gain -12 dB with respect to the typical gain -18 dB with respect to the typical gain 0 0 0 — 0 1 1 0 1 0 — 0 1 0 1 0 1 Speaker receive OFF(SW21 OFF) Speaker receive ON (SW21 ON) Typical receive PAD gain (0 dB) -3 dB with respect to the typical gain -6 dB with respect to the typical gain -9 dB with respect to the typical gain Typical incoming tone gain (0 dB) -10 dB with respect to the typical gain -20 dB with respect to the typical gain Receive PAD = VOL10 Incoming tone gain = VOL11, VOL12 Receive PAD and incoming tone gain are set at a time. At the initial setting, the typical gain is set. At the initial setting, SW21-OFF and the typical gain are set. Remarks Speaker amp. gain = VOL5 Additional speaker gain = VOL6 Speaker amp. gain and additional speaker gain are set at a time. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 — 1 1 0 — 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 1 MSM7502 29/35 ¡ Semiconductor Key scanning signal output control WRITE Mode Address Data AD1 = 1, AD0 = 0 Controlo Data Description for Control The data set on DB7 to DB0 are output on PO7 to PO0 respectively. Output data is held until next data is written. When the set data is set to "0", output data goes to "0", when set to "1", output pin becomes open. At the initial setting, PO7 to PO0 are in open state. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Output Data Key scanning data read out Read Mode Address Data AD1 = 1, AD0 = 0 Contorol Data Description for Control PI2 PI1 PI0 Data input onto PI7 to PI0 are output onto DB7 to DB0. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PI7 PI6 PI5 PI4 PI3 Key scanning interrupt reset WRITE Mode Address Data AD1 = 1, AD0 = 1 Control Data Description for Control INTT output is reset (Output = 1) Remarks Valid during write mode only DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 MSM7502 30/35 ¡ Semiconductor Special functions WRITE Mode Address Data AD1 = 1, AD0 = 1 Contorol Data Description for Control Remarks DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD Deflection Angle Control Voltage Output 0 0 0 0 1 0 0 0 0 1 1 1 1 Power Down Mode Control 0 1 0 0 0 0 0 0 1 1 CODEC Control — 1 1 0 0 0 0 0 1 *2: 0 1 — 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VLCD pin output voltage: 0.0 V : 0.30 V : 0.55 V : 0.85 V : 1.1 V : 1.3 V : 1.5 V : 1.7 V Whole system power down mode Whole system power ON mode CODEC power down mode CODEC power ON mode CODEC operates in m-law CODEC operates in A-law PCMIN and PCMOUT are normally connected PCMOUT is connected to PCMIN At the initial setting stage, set to whole system power down mode. CODEC power ON/OFF control is valid in the whole system power ON mode. At the initial setting stage, set to m-law, and PCMIN and PCMOUT are normally connected. The componding law and the connection control are set at a time. At the initial setting stage, set to 0 V. Even during the whole system power down mode, following functions are available, if XSYNC is input. : Key scanning data I/O, sounder outputs (SA0, SA1), WDT, INTT, and general latch output (LA, LB) MSM7502 31/35 APPLICATION CIRCUIT ¡ Semiconductor +5 V *1 100 kW 0.1 mF 100 kW 0.1 mF MPAI SGT 100 kW TPAI CAO R1I RPO TPAO TPBI MPAO MPBI MPBO TO CAI MLDYI LML +5 V PCMOUT PCMIN BCLOCK XSYNC RSYNC Hold Tone Generator Line Interface Line SGC PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 AG DG VA VD Handset *2 RMI RMO0 RMO1 SPO SPI SAO WRN RDN CEN RESETN DB0 to DB7 AD0 AD1 INTT TIMEN Controller Speaker 0-20 W + +5 V 10 mF 0V 0.1 mF to 1 mF *1 Inserting a capacitor (1 mF to 22 mF) between SGT and AG will improve the transmit path noise characteristic. Insert a resistor if necessary. 0.1 mF SW Matrix *2 MSM7502 32/35 MSM7502 Speech Path Level Setting ¡ Semiconductor TPAO TPBI MPAI MPAO TPAI + MLDYI MPBI MPBO SW1 SW2 SW7 SW16 – 0 dB VOL 1 SW9 SW3 SW4 SW13 SW17 SW14 SW6 SW8 SW18 SW10 TO CAI VOL 9 + 20 dB – –20 dB to +25 dB + 0 dB 5.7 dB VOL 3 VOL 4 – AIN CODEC AOUT VOL 8 CAO R1I R2I RPO RMI SW5 RMO0 0 dB RMO1 – – – VOL 10 PB GEN. Per Wave 0.24 VPP(–21.4 dBV Equivalent) R-Tone GEN. 90 mVPP Pulse (–27.8 dBV Equivalent) F-Tone GEN. 0.16 VPP Pulse (–22.8 dBV Equivalent) S-Tone GEN. 0.22 VPP Pulse (–20.0 dBV Equivalent) CODEC I/O Level Overload Point: 1.2 Vop 0 dBmO : 0.6007 Vrms (–4.4 dBV) VOL 2 VOL 7 –8.7 dB SW5 0 dB 0 dB VOL No. Typical Level Variable Range VOL 1 VOL 2 VOL 3 VOL 4 VOL 5 VOL 6 VOL 7 VOL 8 VOL 9 VOL 10 VOL 11 VOL 12 –6 dB –9 dB –2 dB +4 dB 0 dB 0 dB 0 dB +12 dB +20 dB 0 dB 0 dB 0 dB –14 dB to 0 dB –21 dB to –3 dB –11 dB to –2 dB –5 dB to +4 dB –28 dB to 0 dB –18 dB to 0 dB 90 mV to 180 mV +3 dB to +12 dB +11 dB to +20 dB –9 dB to 0 dB –20 dB to 0 dB –20 dB to 0 dB Step Width 2 dB 3 dB 3 dB 3 dB 4 dB 6 dB 30 mV 3 dB 3,6 dB 3 dB 10 dB 10 dB SPO – VOL 5 VOL 12 VOL 11 –22 dB SW21 SW20 SW11 SW15 – –3 dB –6.8 dB VOL 6 SPI MSM7502 33/35 ¡ Semiconductor MSM7502 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the VA and AG pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Connect the VA pin and the VD pin as close together as possible and route them to the analog 5 V power supply. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. • Connect analog input pins and digital input pins that are not used to the SG pin and to GND, respectively. • When the data is written differently from the data defined in the section, Control Data Description in FUNCTIONAL DESCRIPTION, normal device operation is not guaranteed. 34/35 ¡ Semiconductor MSM7502 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 35/35