MSM7507-01

E2U0019-28-81 ¡ Semiconductor MSM7507-01/02/03 ¡ Semiconductor Single Rail CODEC This version: Aug. 1998 MSM7507-01/02/03 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM7507 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400 Hz with filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for ISDN terminals, digital wireless systems, and digital PBX systems. The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B. The analog output signal, which is of a differential type and can drive a 600 W load, can directly drive a handset receiver. FEATURES • Single power supply: +5 V ± 5% • Low power consumption Operating mode: 20 mW Typ. 40 mW Max. VDD = 5 V Power down mode: 0.03 mW Typ. 0.3 mW Max. VDD = 5 V • ITU-T Companding law MSM7507-01: m/A-law pin selectable MSM7507-02: m-law MSM7507-03: A-law • Transmission characteristics conforms to ITU-T G.714 • Built-in PLL eliminates a master clock • Serial data rate: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz • Adjustable transmit gain • Adjustable receive gain • Built-in reference voltage supply • Analog output can directly drive a 600 W line transformer • The 24-Pin SOP package products provide pin compatibility with the MSM7543/7544 • The 20-Pin SSOP package products have 1/3 the foot print of conventional products • Package options: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7507-01GS-K) (Product name : MSM7507-02GS-K) (Product name : MSM7507-03GS-K) 20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7507-01MS-K) (Product name : MSM7507-02MS-K) (Product name : MSM7507-03MS-K) 1/18 ¡ Semiconductor MSM7507-01/02/03 BLOCK DIAGRAM AIN– AIN+ GSX – + RC LPF 8th BPF AD CONV. AUTO ZERO PCMOUT TCONT PLL XSYNC BCLK SGC SG SG GEN VR GEN RTIM RSYNC (ALAW) PCMIN PDN VDD AG DG VFRO PWI AOUT– – + SG 5th LPF DA CONV. RCONT PWD Logic PWD – + – + SG AOUT+ SG 2/18 ¡ Semiconductor MSM7507-01/02/03 PIN CONFIGURATION (TOP VIEW) SG 1 AOUT+ 2 AOUT– 3 NC 4 PWI 5 VFRO 6 NC 7 VDD 8 DG 9 PDN 10 RSYNC 11 PCMIN 12 24 SGC 23 AIN+ 22 AIN– 21 GSX 20 NC 19 NC 18 (ALAW)* 17 NC 16 AG 15 BCLK 14 XSYNC 13 PCMOUT SG 1 AOUT+ 2 AOUT– 3 PWI 4 VFRO 5 VDD 6 DG 7 PDN 8 RSYNC 9 PCMIN 10 20 SGC 19 AIN+ 18 AIN– 17 GSX 16 NC 15 (ALAW)* 14 AG 13 BCLK 12 XSYNC 11 PCMOUT NC : No connect pin 20-Pin Plastic SSOP NC : No connect pin 24-Pin Plastic SOP * The ALAW pin is only applied to the MSM7507-01GS-K/MSM7507-01MS-K. 3/18 ¡ Semiconductor MSM7507-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp and is used to adjust the level, as shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving and power down modes, the GSX output is at AG voltage. 1) Inverting input type C1 Analog input R1 GSX AIN– AIN+ SG R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) Gain = R2/R1 £ 10 R2 – + 2) Non inverting input type C2 Analog input R5 R4 R3 AIN+ AIN– GSX SG + – R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) Gain = 1 + R4 / R3 £ 10 AG Analog signal ground. VFRO Receive filter output. The output signal has an amplitude of 2.4 VPP above and below the signal ground voltage (SG) when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more. For driving a load of 20 kW or less, connect a resistor of 20 kW or more between the pins VFRO and PWI. When adding the frequency characteristics to the receive signal, refer to the application example. During power saving or power down mode, the output of VFRO is at the voltage level of SG. 4/18 ¡ Semiconductor PWI, AOUT+, AOUT– MSM7507-01/02/03 PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the output of AOUT–. Since the signal from which provides differential drive of an impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a piezoelectric earphone. Refer to the application example. VI Receive Filter VFRO PWI R6 R7 R6 > 20 kW ZL ≥ 1.2 kW Gain = VO/VI = 2 ¥ R7/R6 £ 2 SG – + AOUT– VO ZL SG – + AOUT+ During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high impedance state. The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The output load resistor has a minimum value of 0.6 kW. If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less than that described above. For more details, refer to SINGLE POWER SUPPLY PCM CODEC APPLICATION NOTE. VDD Power supply for +5 V. PCMIN PCM signal input. A serial PCM signal input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLK Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048, or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 5/18 ¡ Semiconductor RSYNC MSM7507-01/02/03 Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are not guaranteed. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 6/18 ¡ Semiconductor DG MSM7507-01/02/03 Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down modes. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7507-03 (A-law) outputs the character signal, inverting the even bits. PCMIN/PCMOUT MSM7507-02 (m-law) MSD +Full scale +0 –0 –Full scale 1000 1111 0111 0000 0000 1111 1111 0000 MSM7507-03 (A-law) MSD 1010 1101 0101 0010 1010 0101 0101 1010 Input/Output Level 7/18 ¡ Semiconductor SG MSM7507-01/02/03 Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is ±300 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power saving or power down modes. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Provides only for the MSM7507-01GS-K/7507-01MS-K. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally pulled down. 8/18 ¡ Semiconductor MSM7507-01/02/03 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition — — — — Rating 0 to 7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Analog Input Voltage Input High Voltage Input Low Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width PCMIN Set-up Time PCMIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width Symbol VDD Ta VAIN VIH VIL FC FS DC tIr tIf tXS tSX tRS tSR tWS tDS tDH RDL CDL Voff — Condition Voltage must be fixed — Min. 4.75 –30 — 2.2 0 Typ. 5.0 +25 — — — Max. 5.25 +85 2.4 VDD 0.8 Unit V °C VPP V V kHz kHz % ns ns ns ns ns ns ms ns ns kW pF mV mV ns Connect AIN– and GSX XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW BCLK XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW BCLKÆXSYNC, See Timing Diagram XSYNCÆBCLK, See Timing Diagram BCLKÆRSYNC, See Timing Diagram RSYNCÆBCLK, See Timing Diagram 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 6.0 40 — — 100 100 100 100 1 BCLK 100 100 0.5 — –100 –10 — 8.0 50 — — — — — — — — — — — — — — 9.0 60 50 50 — — — — 100 — — — 100 +100 +10 500 XSYNC, RSYNC — — Pull-up resistor — Transmit gain stage, Gain = 1 Transmit gain stage, Gain = 10 XSYNC, RSYNC 9/18 ¡ Semiconductor MSM7507-01/02/03 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 Input High Voltage Input Low Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIL VOL IO CIN Condition Operating mode Power-save mode, PDN = 1, XSYNC Æ OFF Power-down mode, PDN = 0 — — — — Pull-up resistance > 500 W — — Min. — — — 2.2 0.0 — — 0.0 — — Typ. 5.0 1.5 0.01 — — — — 0.2 — 5 Max. 10 3.0 0.05 VDD 0.8 2.0 0.5 0.4 10 — Unit mA mA mA V V mA mA V mA pF Transmit Analog Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Gain = 1 Condition AIN+, AIN– GSX with respect to SG Min. 10 20 — –1.2 –20 Typ. — — — — — Max. — — 30 +1.2 +20 Unit MW kW pF V mV Receive Analog Interface Characteristics (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Input Resistance Output Load Resistance Symbol RINPW PWI RLVF RLAO CLVF CLAO VOVF Output Amplitude VOAO VFRO with respect to SG AOUT+, AOUT– (each) with respect to SG VFRO AOUT+, AOUT– VFRO, RL = 20 kW with respect to SG AOUT+, AOUT–, RL = 0.6 kW with respect to SG AOUT+, AOUT–, Gain = 1 with respect to SG Condition Min. 10 20 0.6 — — –1.2 –1.3 –100 –100 Typ. — — — — — — — — — Max. — — — 30 50 +1.2 +1.3 +100 +100 Unit MW kW kW pF pF V V mV mV Output Load Capacitance VOSVF VFRO with respect to SG Offset Voltage VOSAO 10/18 ¡ Semiconductor AC Characteristics MSM7507-01/02/03 (VDD = +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz) Parameter Symbol Loss T1 Loss T2 Transmit Frequency Response Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Receive Frequency Response Loss R3 Loss R4 Loss R5 SD T1 SD T2 SD T3 Transmit Signal to Distortion Ratio SD T4 SD T5 SD R1 SD R2 SD R3 Receive Signal to Distortion Ratio SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 –30 –40 –45 3 0 –30 –40 –45 3 –10 –40 –50 –55 3 –10 –40 –50 –55 –0.3 –0.5 –0.8 –0.3 –0.5 –1.2 –0.3 *1 *2 *2 *1 *2 *2 0 –0.15 –0.15 0.0 35 35 35 29 24 36 36 36 30 25 –0.3 0 Level Condition (dBm0) Min. 20 –0.15 –0.15 –0.15 0 –0.15 Typ. 26 +0.07 Reference –0.04 +0.06 0.4 –0.03 Reference 0.0 +0.05 0.56 43 41 38 31.5 31 27 26 43 41 40 33.5 32 30 27 +0.01 Reference 0 –0.03 +0.15 0 Reference +0.08 +0.12 +0.15 +0.3 +0.5 +0.8 dB +0.3 +0.5 +1.2 +0.3 dB +0.20 +0.20 0.80 — — — — — — — — — — +0.3 dB dB +0.20 +0.20 0.80 +0.20 Max. — +0.20 Unit dB dB dB dB dB dB dB dB dB dB dB *1 Psophometric filter is used *2 Upper is specified for the m-law, lower for the A-law 11/18 ¡ Semiconductor AC Characteristics (Continued) MSM7507-01/02/03 (VDD = +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz) Parameter Symbol Nidle T Nidle R AV T Absolute Level (Initial Difference) AV R AV Tt AV Rt 1020 0 Freq. (Hz) — — Level Condition (dBm0) AIN = SG — *1 *2 — *1 *3 VDD = 5.0 V Ta = 25°C *4 VDD = +5 V ±5% Ta = –30 to 85°C *4 A to A Absolute Delay Td tgd T1 tgd T2 Transmit Group Delay tgd T3 tgd T4 tgd T5 tgd R1 tgd R2 Receive Group Delay tgd R3 tgd R4 tgd R5 Crosstalk Attenuation CR T CR R 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 1020 0 TRANS Æ RECV RECV Æ TRANS Min. — — 0.58 0.58 –0.2 –0.2 Typ. –74.5 –72.5 –78 0.6007 0.6007 — — Max. –70 –69 –75 0.622 Unit Idle Channel Noise dBmOp Vrms 0.622 +0.2 +0.2 dB dB Absolute Level (Deviation of Temperature and Power) 0 BCLK = 64 kHz *5 — — — — — — *5 — — — — — 75 70 — 0.19 0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 80 76 0.60 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 — — ms 0 ms 0 ms dB *1 *2 *3 *4 *5 Psophometric filter is used Upper is specified for the m-law, lower for the A-law Input "0" code to PCMIN AVR is defined at VFRO output Minimum value of the group delay distortion 12/18 ¡ Semiconductor AC Characteristics (Continued) MSM7507-01/02/03 (VDD = +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Symbol Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz S IMD PSR T PSR R tSD Digital Output Delay Time tXD1 tXD2 tXD3 CL = 100 pF + 1 LSTTL 300 to 3400 fa = 470 fb = 320 0 to 50 kHz 0 –4 50 mVPP 4.6 kHz to 100 kHz 2fa – fb *6 Min. 30 — — — 20 20 20 20 Typ. 32 –37.5 –52 30 — — — — Max. — –35 –35 — 200 200 200 200 ns Unit dB dBmO dBmO dB *6 The measurement under idle channel noise 13/18 ¡ Semiconductor TIMING DIAGRAM PCM Data Input/Output Timing Transmit Timing BCLK tXS XSYNC PCMOUT Receive Timing BCLK tRS RSYNC PCMIN
,
, 1 2 3 tSX tWS tXD1 tSD MSD D2 1 2 3 tSR tWS tDS MSD D2 MSM7507-01/02/03 4 5 6 7 8 9 10 11 tXD2 D3 D4 D5 D6 D7 tXD3 D8 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. 4 5 6 7 8 9 10 11 tDH D3 D4 D5 D6 D7 D8 14/18 ¡ Semiconductor MSM7507-01/02/03 APPLICATION CIRCUIT Analog interface MSM7507 AIN– 0.1 mF GSX AIN+ 1:1 Analog output 600 W 300 W 300 W AOUT– PWI VFRO 51 kW SGC 0.1 mF 0V +5 V 10 mF 0–20W – + Digital interface +5 V 1:1 Analog input 600 W 51 kW PCMOUT XSYNC RSYNC BCLK PCMIN PDN PCM signal output 8 kHz SYNC signal input SG AOUT+ PCM shift clock input PCM data input Power Down control input AG 1 mF VDD DG FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT Microphone amp M C1 C2 R2 GSX AIN+ SG AOUT+ R5 C4 R4 AOUT– PWI VFRO R3 C3 Receive frequency characteristic Adjustment determined with C3, C4, R3, R4 R1 AIN– Transmit frequency characteristic Adjustment determined with C1, C2, R1, R2 15/18 ¡ Semiconductor MSM7507-01/02/03 RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 16/18 ¡ Semiconductor MSM7507-01/02/03 PACKAGE DIMENSIONS (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/18 ¡ Semiconductor MSM7507-01/02/03 (Unit : mm) SSOP20-P-250-0.95-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.18 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18