MSM7508B

E2U0013-28-81 ¡ Semiconductor MSM7508B/7509B ¡ Semiconductor Single Rail CODEC This version: Aug. 1998 MSM7508B/7509B Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM7508B and MSM7509B are single-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices are optimized for telephone terminals in ISDN and digital wireless systems. The MSM7508B/MSM7509B are the transmission-clocks extended versions of the MSM7508/ MSM7509. It is recommended to use the MSM7508/MSM7509 for the transmission clocks of 64, 128, 256kHz. FEATURES • Single power supply: +5 V ± 5% • Low power consumption Operating mode: 17.5 mW Typ. 37 mW Max. Power down mode: 1.5 mW Typ. 3 mW Max. • ITU-T Companding law MSM7508B: m-law MSM7509B: A-law • Built-in PLL eliminates a master clock • Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz • Adjustable transmit gain • Built-in reference voltage supply • Package options: 16-pin plastic DIP (DIP16-P-300-2.54-W1) (Product name : MSM7508BRS) (Product name : MSM7509BRS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7508BGS-K) (Product name : MSM7509BGS-K) 28-pin plastic QFJ (PLCC) (QFJ28-P-S450-1.27) (Product name : MSM7508BJS) (Product name : MSM7509BJS) Note: The product names are indicated in PIN CONFIGURATION. 1/17 ¡ Semiconductor MSM7508B/7509B BLOCK DIAGRAM AIN+ AIN– GSX SGC SG + – RC Active BPF (8th) AD Conv. Auto Zero Transmit Controller PCMOUT XSYNC BCLOCK Signal Ground Voltage Ref. LPF (5th) TPLL RPLL DA Conv. PWD Logic Receive Controller RSYNC PCMIN PDN VDD AG DG AOUT + – PWD 2/17 ¡ Semiconductor MSM7508B/7509B PIN CONFIGURATION (TOP VIEW) SGC 1 SG 2 AOUT 3 VDD 4 DG 5 PDN 6 RSYNC 7 PCMIN 8 16 AIN+ 15 AIN– 14 GSX 13 NC 12 AG 11 BCLOCK 10 XSYNC 9 PCMOUT SGC 1 NC 2 SG 3 NC 4 AOUT 5 VDD 6 DG 7 NC 8 NC 9 24 AIN+ 23 AIN– 22 NC 21 GSX 20 NC 19 NC 18 AG 17 NC 16 BCLOCK 15 NC 14 XSYNC 13 PCMOUT NC : No connect pin 16-Pin Plastic DIP PDN 10 RSYNC 11 PCMIN 12 NC : No connect pin 4 AOUT 28 AIN+ 27 AIN– 26 GSX 1 SGC 3 NC 2 SG 24-Pin Plastic SOP VDD 5 NC 6 NC 7 NC 8 NC 9 NC 10 DG 11 PDN 12 RSYNC 13 PCMIN 14 NC 15 PCMOUT 16 XSYNC 17 BCLOCK 18 25 NC 24 NC 23 NC 22 NC 21 NC 20 NC 19 AG NC : No connect pin 28-Pin Plastic QFJ (PLCC) 3/17 ¡ Semiconductor MSM7508B/7509B PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp and is used to adjust the level, as shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving and power down modes, the GSX output is in a high impedance state. 1) Inverting input type C1 Analog input R1 GSX AIN– AIN+ SG R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) Gain = R2/R1 £ 10 R2 – + 2) Non inverting input type C2 Analog input R5 R4 R3 AIN+ AIN– GSX SG + – R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) Gain = 1 + R4 / R3 £ 10 AG Analog signal ground. AOUT Analog output. The output signal amplitude is a maximum of 2.4 VPP above and below the signal ground voltage level (VDD/2). The output load resistance is a minimum of 20 kW. During power saving or power down mode, the output of AOUT is at the voltage level of signal ground. 4/17 ¡ Semiconductor VDD Power supply for +5 V. PCMIN MSM7508B/7509B PCM signal input. A serial PCM signal input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLOCK signal. The data rate of the PCM signal is equal to the frequency of the BCLOCK signal. The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLOCK Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 5/17 ¡ Semiconductor DG MSM7508B/7509B Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLOCK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLOCK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down modes. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7509B (A-law) outputs the character signal, inverting the even bits. PCMIN/PCMOUT MSM7508B (m-law) MSD +Full scale +0 –0 –Full scale 1000 1111 0111 0000 0000 1111 1111 0000 MSD 1010 1101 0101 0010 1010 0101 0101 1010 MSM7509B (A-law) Input/Output Level SG Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is ±300 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power saving or power down modes. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. 6/17 ¡ Semiconductor MSM7508B/7509B ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition — — — — Rating 0 to 7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Analog Input Voltage Input High Voltage Input Low Voltage Symbol VDD Ta VAIN VIH VIL Condition Voltage must be fixed — Min. 4.75 –10 — 2.2 0 Typ. 5.0 +25 — — — Max. 5.25 +70 2.4 VDD 0.8 Unit V °C VPP V V Connect AIN– and GSX XSYNC, RSYNC, BCLOCK, PCMIN, PDN 64, 128, 256, 512, 1024, Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width PCMIN Set-up Time PCMIN Hold Time Analog Output Load FC FS DC tIr tIf tXS tSX tRS tSR tWS tDS tDH RAL CAL Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width RDL CDL Voff — AOUT GSX AOUT, GSX Pull-up resistor — Transmit gain stage, Gain = 1 Transmit gain stage, Gain = 10 XSYNC, RSYNC, BCLOCK BCLOCK XSYNC, RSYNC BCLOCK XSYNC, RSYNC, BCLOCK, PCMIN, PDN BCLOCKÆXSYNC, See Timing Diagram XSYNCÆBCLOCK, See Timing Diagram BCLOCKÆRSYNC, See Timing Diagram RSYNCÆBCLOCK, See Timing Diagram 2048, 96, 192, 384, 768, 1536, 1544, 200 7.0 40 — — 100 100 100 100 1 BCLK 100 100 20 20 — 0.5 — –100 –10 — 8.0 50 — — — — — — — — — — — — — — — — — 10.0 60 50 50 — — — — 100 — — — — 100 — 100 +100 +10 500 kHz kHz % ns ns ns ns ns ns ms ns ns kW kW pF kW pF mV mV ns XSYNC, RSYNC — — 7/17 ¡ Semiconductor MSM7508B/7509B ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 Input High Voltage Input Low Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Analog Output Offset Veltage Input Capacitance Analog Input Resistance VIH VIL IIH IIL VOL IO VOFF CIN RIN AIN+, AIN– Condition Operating mode Power-down mode, PDN = 0 Power-save mode, PDN = 1, SYNC Æ OFF — — — — Pull-up resistance > 500 W — AOUT with respect to SG — Min. — — — 2.2 0.0 — — 0.0 — –100 — — Typ. 3.5 0.3 0.8 — — — — 0.2 — — 5 10 Max. 7.0 0.5 1.2 VDD 0.8 2.0 0.5 0.4 10 +100 — — Unit mA mA mA V V mA mA V mA mV pF MW 8/17 ¡ Semiconductor AC Characteristics MSM7508B/7509B (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Loss T1 Loss T2 Transmit Frequency Response Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Receive Frequency Response Loss R3 Loss R4 Loss R5 SD T1 SD T2 SD T3 Transmit Signal to Distortion Ratio SD T4 SD T5 SD R1 SD R2 SD R3 Receive Signal to Distortion Ratio SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 –30 –40 *1 –45 3 0 –30 –40 *1 –45 3 –10 –40 –50 –55 3 –10 –40 –50 –55 –0.2 –0.4 –0.8 –0.2 –0.4 –1.2 –0.2 *2 25 24 –0.2 *2 23 36 36 36 30 0 –0.15 –0.15 0.0 35 35 35 28 0 Level Condition (dBm0) Min. 20 –0.15 –0.15 –0.15 0 –0.15 Typ. 26 +0.07 Reference –0.04 +0.06 0.40 –0.03 Reference –0.02 +0.15 0.56 43 41 38 30.0 29.5 25.0 24.5 43 41 40 33.5 32 30 27 +0.01 Reference 0.0 –0.03 +0.15 0 Reference –0.06 –0.20 –0.27 +0.2 +0.4 +0.8 dB +0.2 +0.4 +1.2 +0.2 dB +0.20 +0.20 0.80 — — — — — — — — — — +0.2 dB dB +0.20 +0.20 0.80 +0.20 Max. — +0.20 Unit dB dB dB dB dB dB dB dB dB dB dB *1 Psophometric filter is used *2 Upper is specified for the MSM7508B, lower for the MSM7509B 9/17 ¡ Semiconductor AC Characteristics (Continued) MSM7508B/7509B (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Symbol Nidle T Nidle R AV T Absolute Level (Initial Difference) AV R A to A Absolute Delay Td tgd T1 tgd T2 Transmit Group Delay tgd T3 tgd T4 tgd T5 tgd R1 tgd R2 Receive Group Delay tgd R3 tgd R4 tgd R5 Crosstalk Attenuation CR T CR R 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 1020 0 TRANS Æ RECV RECV Æ TRANS Freq. (Hz) — — 1020 Idle Channel Noise Level Condition (dBm0) AIN = SG — *1 *2 — 0 *2 *3 Min. — — 0.5671 0.5671 Typ. –72.5 –70.5 –76.5 0.6007 0.6007 Max. –70 –69 –74 0.6363 Unit dBmOp Vrms 0.6363 0 BCLOCK = 64 kHz *4 — — — — — — — 0.19 0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 85 77 0.60 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 — — ms 0 ms *4 0 — — — — — 75 70 ms dB *1 *2 *3 *4 Psophometric filter is used Upper is specified for the MSM7508B, lower for the MSM7509B MSM7508B: All "0" code to PCMIN, MSM7509B: "11010101" to PCMIN Minimum value of the group delay distortion 10/17 ¡ Semiconductor AC Characteristics (Continued) MSM7508B/7509B (VDD = +5 V ±5%, Ta = –10°C to +70°C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Symbol Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz S IMD PSR T PSR R tSD Digital Output Delay Time tXD1 tXD2 tXD3 CL = 100 pF + 1 LSTTL 300 to 3400 fa = 470 fb = 320 0 kHz to 50 kHz 0 –4 50 mVPP 4.6 kHz to 100 kHz 2fa – fb *5 Min. 30 — — — 50 50 50 50 Typ. 32 –37.5 –52 30 — — — — Max. — –35 –35 — 200 200 200 200 ns Unit dB dBmO dBmO dB *5 The measurement under idle channel noise 11/17 ¡ Semiconductor TIMING DIAGRAM PCM Data Input/Output Timing Transmit Timing BCLOCK tXS XSYNC PCMOUT Receive Timing BCLOCK tRS RSYNC PCMIN
,
, 1 2 3 tSX tWS tXD1 tSD MSD D2 1 2 3 tSR tWS tDS MSD D2 MSM7508B/7509B 4 5 6 7 8 9 10 11 tXD2 D3 D4 D5 D6 D7 tXD3 D8 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. 4 5 6 7 8 9 10 11 tDH D3 D4 D5 D6 D7 D8 12/17 ¡ Semiconductor MSM7508B/7509B APPLICATION CIRCUIT MSM7508B/7509B Analog input AIN– GSX Analog output AOUT AIN+ SG 0.1 mF SGC AG 0V – 10 mF + +5 V 0 to 20W 1 mF VDD DG RSYNC PDN Power Down control input "1" = Operation "0" = Power down XSYNC 8 kHz SYNC signal input PCMIN BCLOCK PCM data input PCM shift clock input PCMOUT 1 kW +5 V Digital interface PCM signal output The analog output signal has an amplitude of ± 1.2 V above and below the offset voltage level of VDD/2. 13/17 ¡ Semiconductor MSM7508B/7509B RECOMMENDATIONS FOR ACTUAL DESIGN • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 14/17 ¡ Semiconductor MSM7508B/7509B PACKAGE DIMENSIONS (Unit : mm) DIP16-P-300-2.54-W1 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.00 TYP. 15/17 ¡ Semiconductor MSM7508B/7509B (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM7508B/7509B (Unit : mm) QFJ28-P-S450-1.27 Spherical surface Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 1.00 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17