MSM7603B

E2U0064-18-82 ¡ Semiconductor MSM7603/7603B ¡ Semiconductor Echo Canceler This version: Aug. 1998 MSM7603/7603B GENERAL DESCRIPTION The MSM7603/7603B is an improved version of the MSM7602 with basically the same configuration, and offers twice the cancelable echo delay time of the MSM7602. The MSM7603B I/O interface allows switching between m-law PCM and A-law PCM. The MSM7603/7603B is a low-power CMOS IC device for canceling echo (in an acoustic system or telephone line) generated in a speech path. Echo is canceled, in digital signal processing, by estimating the echo path and generating a pseudo echo signal. When used as an acoustic echo canceler, the device can cancel the acoustic echo, between the loud speaker and the microphone, which occur during hands free communication such as on a cellular phone or a conference system phone. When used as a line echo canceler, the device can cancel the line echo which returns due to impedance mismatching in a hybrid. In addition, a quality conversation is made possible by controlling the level and by preventing howling through a howling detector, double talk detector, attenuation function and a gain control function, and by controlling the low level noise by means of a center clipping function. The use of a single chip codec, such as the MSM7704 (3 V) and MSM7533 (5 V), allows an economic and efficient echo canceler to be configured. FEATURES • Can handle both acoustic and telephone line echoes. • Switchable between m-law PCM and A-law PCM interfaces. (MSM7603B) • Cancelable echo delay time: MSM7603B-003 .............. 55 ms (max.) • Echo attenuation : 30 dB (typ.) • Clock frequency : 19.2 MHz 17.5 MHz to 20 MHz (when internal sync signal not used) • Power supply voltage : 2.7 V to 5.5 V • Package: 28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : MSM7603-003GS-K) (Product name : MSM7603B-003GS-K) 1/20 ¡ Semiconductor MSM7603/7603B BLOCK DIAGRAM MSM7603/7603B RIN S/P Non–linear/ Linear ATT Gain Linear/ Non–linear P/S ROUT Howling Detector Double Talk Detector Power Calculator Adaptive FIR Filter (AFF) – SOUT P/S Linear/ Non–linear Center Clip ATT + + Non–linear/ Linear S/P SIN RST PWDWN Clock Generator Mode Selector PLL I/O Controller VDD VSS CLKIN SCKO SYNCO NLP HCL ADP ATT GC HD m/A SCK SYNC * For MSM7603B only 2/20 ¡ Semiconductor MSM7603/7603B PIN CONFIGURATION (TOP VIEW) NLP 1 HCL 2 ADP 3 SYNC 4 SCK 5 VDD 6 VSS 7 RST 8 PWDWN 9 HD 10 VDD[m/A]* 11 CLKIN 12 VDD(PLL) 13 VSS(PLL) 14 28 VDD 27 SOUT 26 ROUT 25 SIN 24 RIN 23 VSS 22 NC 21 NC[TEST]* 20 VDD 19 ATT 18 SCKO 17 GC 16 SYNCO 15 VSS NC : No connect pin 28-Pin Plastic SSOP * Pins shown in brackets apply to MSM7603B. 3/20 ¡ Semiconductor MSM7603/7603B PIN DESCRIPTIONS Pin 1 Symbol NLP Type I Description This is the control pin for the center clipping function to force the SOUT output to a minimum value when the SOUT signal is below –57 dBm0. Effective for reducing low-level noise. "H": Center clip ON "L": Center clip OFF 2 HCL I This is the through mode control pin. When this pin is in the through mode the RIN and SIN data are output to ROUT and SOUT. At the same time, the coefficient of the adaptive FIR filter is cleared. "H": Through mode "L": Normal mode (echo canceler operates) 3 ADP I This is the AFF coefficient control pin which stops updating the adaptive FIR filter (AFF) coefficient and sets it to a fixed value, when the pin is configured to be the coefficient fix mode. Used when holding the AFF coefficient which has been once converged. "H": Coefficient fix mode "L": Normal mode (coefficient update) 4 SYNC I This is the input pin for the sync signal for transmit/receive serial data. This pin uses the external SYNC or SYNCO. Inputs the PCM codec transmit/receive sync signal (8 kHz). 5 SCK I This is the clock input pin for transmit/receive serial data. It uses the external SCK or the SCKO. Input the PCM codec transmit/receive clock (64 to 2048 kHz). 4/20 ¡ Semiconductor MSM7603/7603B PIN DESCRIPTIONS (Continued) Pin 8 Symbol RST Type I Description This is the input pin for the reset signal. "L": Reset mode "H": Normal operation mode Due to initialization, input signals are disabled for 100 ms after reset (after RST is returned from "L" to "H"). Input the basic clock during the reset. Output pins during the reset are in the following sates : High impedance: SOUT, ROUT Not affected: SYNCO, SCKO 9 PWDWN I This is the power-down mode control pin for power down operation "L": Power-down mode "H": Normal operation mode During power-down mode, all input pins are disabled and output pins are in the following states : High impedance : SOUT, ROUT "L": SYNCO, SCKO Reset after the power-down mode is released. 10 HD I This pin controls the howling detect function that detects and cancels a howling generated during hands-free talking for acoustic system. This function is used to cancel acoustic echoes. "L": Howling detector ON "H": Howling detector OFF 11 (m/A) I Used for MSM7603B only. This is the input pin for m-law PCM/A-law PCM interface select signal. "L": A-law PCM interface "H": m-law PCM interface For MSM7603, apply VDD. 12 CLKIN I This is the input pin for external input for the basic clock. Input the basic clock (17.5 to 20 MHz). When the internal sync signal (SYNCO, SCKO) is used, input the basic clock of 19.2 MHz. 13 VDD (PLL) I This is the power supply pin for the PLL circuit used for the basic clock. Insert a 0.1 mF capacitor with excellent high frequency characteristics between VDD (PLL) and VSS (PLL). 14 16 VSS (PLL) SYNCO I O This is the ground pin for the PLL circuit used for the basic clock. This is the output pin for the 8 kHz sync signal for the PCM codec. Connect to the SYNC pin and the PCM codec transmit/receive sync pin. Leave open if using an external SYNC. 5/20 ¡ Semiconductor MSM7603/7603B PIN DESCRIPTIONS (Continued) Pin 17 Symbol GC Type I Description This is the pin for the input signal by which the gain controller for the RIN input is controlled. The pin also controls RIN input level and prevents howling. The gain controller adjusts the RIN input level when it is –20 dBm0 or above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to –20 dBm0 in the attenuation range from 0 to 8.5 dB. RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB. "H": Gain control ON "L": Gain control OFF "H" is recommended for performing echo cancellation. 18 SCKO O This is the output pin for the transmit clock signal (256 kHz) for the PCM codec. Connect to the SCK pin and the PCM codec transmit/receive clock pin. Leave open when using an external SCK. 19 ATT I This is the control pin for the ATT function which prevents howling by attenuators (ATT) for the RIN input and SOUT output. If there is input only to RIN, then the ATT for the SOUT output is activated. If there is no input to SIN or there is input to both SIN and RIN, then the ATT for the RIN input is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. "H": ATT OFF "L": ATT ON "L" is recommended for performing echo cancellation. 21 24 (TEST) RIN O I This pin is for MSM7603B only and not used. Should be left open. In MSM7603 it is an NC pin. This is the receive serial data input pin. Input the PCM signal synchronized to SYNC and SCK. Data is read at the falling edge of SCK. 25 SIN I This is the transmit serial data input pin. Input the PCM signal synchronized to SYNC and SCK. Data is read at the falling edge of SCK. 26 ROUT O This is the output pin for receive serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in high impedance state during the absence of data output. 27 SOUT O This is the output pin for transmit serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in high impedance state during the absence of data output. 6/20 ¡ Semiconductor MSM7603/7603B ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG — Ta = 25˚C Condition Rating –0.3 to + 7 –0.3 to VDD + 0.3 1 –55 to +150 Unit V V W ˚C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Power Supply Voltage High Level Input Voltage Low Level Input Voltage Operating Temperature Symbol VDD VSS VIH VIL Ta Condition — — — — — Min. 2.7 — 2.0 0 –40 (VDD = 2.7 V to 3.6 V) Typ. 3.3 0 — — +25 Max. 3.6 — VDD 0.5 +85 Unit V V V V ˚C (VDD = 4.5 V to 5.5 V) Parameter Power Supply Voltage Power Supply Voltage High Level Input Voltage Low Level Input Voltage Operating Temperature Symbol VDD VSS VIH VIL Ta Condition — — — — — Min. 4.5 — 2.4 0 –40 Typ. 5 0 — — +25 Max. 5.5 — VDD 0.8 +85 Unit V V V V ˚C 7/20 ¡ Semiconductor MSM7603/7603B ELECTRICAL CHARACTERISTICS DC Characteristics Parameter High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Output Leakage Current Low Level Output Leakage Current Power Supply Current (Operating) Power Supply Current (Standby) Input Capacitance Output Load Capacitance Symbol VOH VOL IIH IIL IOZH IOZL IDDO IDDS CI CLOAD PWDWN = "L" — — Condition IOH = 40 mA IOL = 1.6 mA VIH = VDD VIL = VSS VOH = VDD VOL = VSS — (VDD = 2.7 V to 3.6 V, Ta = –40˚C to +85˚C) Min. 2.2 0 — –1 — –1 — — — — Typ. — — 0.1 –0.1 0.1 –0.1 30 0.5 — — Max. VDD 0.4 1 — 1 — 50 1 15 20 Unit V V mA mA mA mA mA mA pF pF (VDD = 4.5 V to 5.5 V, Ta = –40˚C to +85˚C) Parameter High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Output Leakage Current Low Level Output Leakage Current Power Supply Current (Operating) Power Supply Current (Standby) Input Capacitance Output Load Capacitance Symbol VOH VOL IIH IIL IOZH IOZL IDDO IDDS CI CLOAD Condition IOH = 40 mA IOL = 1.6 mA VIH = VDD VIL = VSS VOH = VDD VOL = VSS — PWDWN = "L" — — Min. 4.2 0 — –10 — –10 — — — — Typ. — — 0.1 –0.1 0.1 –0.1 40 0.5 — — Max. VDD 0.4 10 — 10 — 70 1 15 20 Unit V V mA mA mA mA mA mA pF pF 8/20 ¡ Semiconductor Echo Canceler Characteristics (Refer to Characteristics Diagram) Parameter Symbol Condition RIN = –10 dBm0 (5 kHz band white noise) Echo Attenuation LRES E. R. L. (echo return loss) = 6 dB TD = 50 ms ATT, GC, NLP: OFF RIN = –10 dBm0 Cancelable Echo Delay Time TD (5 kHz band white noise) E. R. L. = 6 dB ATT, GC, NLP: OFF — — — 30 Min. MSM7603/7603B Typ. Max. Unit — dB 55 ms 9/20 ¡ Semiconductor AC Characteristics Parameter Clock Frequency When Internal Sync Signal is not used Clock Cycle Time When Internal Sync Signal is not used Clock Duty Ratio Clock "H" Level Pulse Width fc = 19.2 MHz Clock "L" Level Pulse Width fc = 19.2 MHz Clock Rise Time Clock Fall Time Sync Clock Output Time Internal Sync Clock Frequency Internal Sync Clock Output Cycle Time Internal Sync Clock Duty Ratio Internal Sync Signal Output Delay Time Internal Sync Signal Period Internal Sync Signal Output Width Transmit/Receive Sync Clock Frequency Transmit/Receive Sync Clock Cycle Time Transmit/Receive Sync Clock Duty Ratio Transmit/Receive Sync Signal Period Sync Timing Sync Signal Width Receive Signal Setup Time Receive Signal Hold Time Receive Data Input Time Serial Output Delay Time Reset Signal Input Width Reset Start Time Reset End Time Processing Operation Start Time Power Down Start Time Power Down End Time Control Pin Setup Time (RST) Control Pin Hold Time (RST) Control Pin Setup Time Control Pin Hold Time Symbol fC tMCK tDMC tMCH tMCL tr tf tDCM fCO tCO tDCO tDCC tCYO tWSO fSCK tSCK tDSC tCYC tXS tSX tWSY tDS tDH tID tSD tXD tWR tDRS tDRE tDIT tDPS tDPE tDSR tDHR tDTS tDTH VDD = 2.7 V to 3.6 V Min. — 17.5 — 50.0 40 20.8 20.8 — — — — — — — — — 64 0.488 40 123 45 45 tSCK 45 45 — — — 1 5 — 100 — — 10 20 20 0 160 Typ. 19.2 — 52.08 — — — — — — — 256 3.9 50 — 125 tCO — — 50 125 — — — — — 7tSCK — — — — — — — — — — — — — Max. — 20.0 — 57.14 60 31.3 31.3 5 5 40 — — — 5 — — 2048 15.6 60 — — tCYC-tSCK — — — — 90 90 — — 52 — 111 15 — — — — — MSM7603/7603B (Ta = –40˚C to +85˚C) VDD = 4.5 V to 5.5 V Min. — 17.5 — 50.0 40 20.8 20.8 — — — — — — — — — 64 0.488 40 123 45 45 tSCK 45 45 — — — 1 5 — 100 — — 10 20 20 0 160 Typ. 19.2 — 52.08 — — — — — — — 256 3.9 50 — 125 tCO — — 50 125 — — — — — 7tSCK — — — — — — — — — — — — — Max. — 20.0 — 57.14 60 31.3 31.3 5 5 40 — — — 5 — — 2048 15.6 60 — — tCYC-tSCK — — — — 90 90 — — 52 — 111 15 — — — — — Unit MHz ns ns ns ns ns ns ns kHz ms % ns ms ms kHz ms % ms ns ns ms ns ns ms ns ns ms ns ns ms ns ns ns ns ns ns ns Reset Pulse Width Immediately after Power Down tWPR 10/20 ¡ Semiconductor MSM7603/7603B TIMING DIAGRAM Clock Timing fC, tMCK, tDMC CLKIN tDCM SCKO fCO, tCO SCKO tDCC tDCC tCYO SYNCO tWSO tDCO tDCM tMCH tMCL tr tf Serial Input Timing fSCK, tSCK SCK tXS tSX tCYC tDSC SYNC tWSY tDS SIN RIN MSB 7 tDH LSB 0 MSB 7 6 5 4 tID 3 2 1 11/20 ¡ Semiconductor Serial Output Timing MSM7603/7603B fSCK, tSCK SCK tXS tSX tCYC tDSC SYNC SOUT ROUT Operation Timing After Reset tWR RST Internal operaion Power Down Timing PWDWN Internal Operation RST  

,          tSD tXD tWSY tXD High-Z MSB 7 6 5 4 3 2 1 LSB High-Z 0 MSB 7 *Reset timing can be asynchronous. tDIT tDRS tDRE Reset Initialization Processing Start * INT is invalid during the shaded interval. tDPS tDPE Power Down Processing Start tWPR Invalid 12/20 ¡ Semiconductor Control Pin Load-in Timing MSM7603/7603B tWR RST tDSR NLP, HCL, HD, ATT, ADP, GC tDHR SCK tCYC SYNC SIN RIN MSB 7 6 5 4 tID 3 2 1 LSB 0 tDTH MSB 7 tDTS NLP, HCL, HD, ATT, ADP, GC 13/20 ¡ Semiconductor MSM7603/7603B HOW TO USE THE MSM7603/7603B The MSM7603/7603B cancels, based on the RIN signal, the echo which returns to SIN. Connect the base signal to the R side and the echo-generated signal to the S side. Connection Methods According to Echoes Example 1: Canceling acoustic echo (to handle acoustic echo from line input) MSM7603 MSM7603B ROUT Acoustic echo AFF CODEC SIN RIN H Line input + – + CODEC SOUT Example 2: Canceling line echo (to handle line echo from microphone input) MSM7603 MSM7603B RIN AFF CODEC SOUT ROUT H Microphone input – + + SIN CODEC Lin echo Example 3: Canceling of both acoustic and line echo (to handle both acoustic echo from line input and line echo from microphone input) MSM7603 MSM7603B ROUT Acoustic echo CODEC AFF SIN RIN SOUT MSM7603 MSM7603B SIN Line input + – + SOUT RIN AFF Microphone input For acoustic echo For line echo + ROUT CODEC H Line echo + – 14/20 ¡ Semiconductor MSM7603/7603B ECHO CANCELER CHARACTERISTICS DIAGRAM (for m-law and A-law, and for reference only) E. R. L. vs. echo attenuation 40 30 20 10 0 40 30 20 10 0 RIN input level vs. echo attenuation Echo attenuation [dB] 40 30 20 10 0 Echo attenuation [dB] –10 –50 –40 –30 –20 –10 RIN input level [dBm0] Measurement Conditions : RIN input: 5 kHz band white noise Echo delay time TD = 50 ms E.R.L. = 6 dB ATT, GC, NLP = OFF Power supply voltage 5 V 0 E. R. L. [dB] Measurement Conditions : RIN input = –10 dBm0 5 kHz band white noise Echo delay time TD = 50 ms ATT, GC, NLP = OFF Power supply voltage 5 V Echo delay time vs. echo attenuation 30 Echo attenuation [dB] 20 10 0 0 10 20 30 40 50 Measurement Conditions : RIN input = –10 dBm 5 kHz band white noise E.R.L. = 6 dB ATT, GC, NLP = OFF Power supply voltage 5 V Echo delay time [ms] Note: Above characteristics are for the MSM7533 (VDD 5 V, m-law CODEC interface). For the MSM7704 (VDD 3 V, m-law interface) the characteristics are basically the same except for input and output levels. Refer to the PCM CODEC data sheet. MSM7533 (for both transmit and receive) 0 dBm0 = 0.85 Vrms = 0.8 dBm (600 W) MSM7704 (for transmit side) 0 dBm0 = 0.35 Vrms = –6.9 dBm (600 W) (for receive side) 0 dBm0 = 0.5 Vrms = –3.8 dBm (600 W) 15/20 ¡ Semiconductor Measurement System Block Diagram White noise generator L. P. F. RIN 5 kHz RIN ROUT MSM7603/7603B TD Delay Echo delay time ATT E. R. L. (Echo Return Loss) MSM7603 MSM7603B Level meter SOUT SOUT Power supply voltage 5 V 2ch CODEC MSM7533 SIN 16/20 ¡ Semiconductor MSM7603/7603B APPLICATION CIRCUIT Bidirectional Connection Example 2ch CODEC MSM7533VGS-K R2 DV R3 21 AIN1 22 GSX1 4 AOUT1 13 12 14 10 16 19 5 6 DOUT1 DIN1 XSYNC RSYNC BCLK A/m PDN CHP 24 AIN2 23 GSX2 2 AOUT2 14 DOUT2 11 DIN2 8 VDD 1 SGC AG DG 18 C9 9 + C10 C11 (AG) AV R6 R7 DV Microphone input C1 R1 R5 C5 Line input Line output Speaker output DV DV R4 For cancelation of acoustic echo MSM7603/7603B 25 SIN 26 ROUT 4 SYNC 5 SCK 16 SYNCO 18 SCKO 27 SOUT 24 RIN NLP HCL ADP ATT GC HD (m / A) (TEST) VDD(P) VSS(P) VSS VSS VSS C2 C3 DV R9 R10 DV For cancelation of line echo MSM7603/7603B 27 SOUT 24 RIN DV 1 2 3 19 17 10 11 21 C8 13 14 7 15 23 NLP HCL ADP ATT GC HD (m / A) (TEST) VDD(P) VSS(P) VSS VSS VSS C6 C7 25 SIN 26 ROUT 4 SYNC 5 SCK 16 SYNCO 18 SCKO 9 PWDWN 8 RST 12 CLKIN 6 VDD VDD 20 VDD 28 + DV DV R8 PWDWN RST CLK DV 9 PWDWN 8 RST 12 CLKIN 6 VDD 20 V DD 28 V DD + DV 1 2 3 19 17 10 11 21 13 C4 14 7 15 23 DV R1=20 kW R2=20 kW R3=2.2 kW R4=10 kW R9=10 kW C1=1 mF C2=10 mF C3=0.1 mF C4=0.1 mF R5=20 kW R6=20 kW R7=2.2 kW R8=10 kW R10=10 kW C5=1 mF C6=10 mF C7=0.1 mF C8=0.1 mF C9=0.1 mF C10=10 mF C11=0.1 mF Use the MSM7704-01GS-VK as a PCM CODEC when VDD 3 V is used. The MSM7533 is pin compatible with the MSM7704. 17/20 ¡ Semiconductor MSM7603/7603B NOTES ON USE 1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be amplified, the echo cannot be eliminated. Refer to the characteristics diagram for E. R. L. vs. echo attenuation quantity. 2. Set the level of the analog input so that the PCM codec does not overflow. 3. The recommended input level is –10 to –20 dBm0. Refer to the characteristics diagram for the RIN input level vs. echo attenuation quantity. 4. Applying the tone signal to this echo canceler for long duration may decrease echo attenuation. When used with the HD pin "L" (howling detector ON), this echo canceler may operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher level than the signal being input to RIN is input to the SIN pin. A signal should therefore be input either to the RIN pin or to the SIN pin. If, however, the tone signal is input to the SIN pin while a signal is input to the RIN pin, the ADP, HD, or HCL pin must be set to "H". 5. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset each time. 6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock simultaneously with power ON. If the device is put into power down mode immediately after power ON, be sure to input 10 or more clocks of the basic clock before setting to the power down mode. 7. After power ON, be sure to reset the device. 8. After the power down mode is released (when PWDWN pin is changed to a "1" from a "0"), be sure to reset the device. 9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 dB. 18/20 ¡ Semiconductor MSM7603/7603B EXPLANATION OF TERMS Attenuating Function : This function prevents howling and controls the noise level with the attenuator for the RIN input and SOUT output. Refer to the explanation of pins (ATT pin). Echo Attenuation : If there is talking (input only to RIN) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. Echo attenuation = (SOUT level during through mode operation) – (SOUT level during echo canceler operation) [dB] Echo Delay Time : This is the time from when the signal is output from ROUT until it returns to SIN as an echo. Acoustic Echo : When using a hands-free phone, for example, the signal output from the speaker echoes and is input again to the microphone. The return signal is referred to as acoustic echo. Telephone Line Echo : This is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. Gain Control Function : This function prevents howling and controls the sound level by with a gain controller for the RIN input. Refer to the explanation of pins (GC pin). Center Clipping Function : This function forces the SOUT output to a minimum value when the signal is below –57 dBm0. Refer to the explanation of pins (NLP pin). Double Talk Detection : Double talk refers to a state in which the SIN and RIN signals are input simultaneously. In a double talk state, a signal other than the echo signal which is to be canceled can be input to the SIN input, resulting in malfunction. The double talk detector prevents such malfunction of the canceler. Howling Detection : This is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands-free talking. Howling not only interferes with talking, but can also cause malfunction of the echo canceler. The howling detector prevents such malfunction and howling. Echo Return Loss (ERL) : When the signal output from ROUT returns to SIN as an echo, ERL refers to how much loss there is in the signal level during ROUT. ERL = (ROUT level) – (SIN level of the ROUT signal which returns as an echo) [dB] If ERL is positive (ROUT > SIN), acts as an attenuator. If ERL is negative (ROUT < SIN), acts as an amplifier. PHS : Personal Handyphone System 19/20 ¡ Semiconductor MSM7603/7603B PACKAGE DIMENSIONS (Unit : mm) SSOP28-P-485-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.39 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 20/20