MSM7652

¡ Semiconductor MSM7652 ¡ Semiconductor NTSC/PAL Digital Video Encoder This version: Jun. 1998 MSM7652 in im el Pr y ar GENERAL DESCRIPTION The MSM7652 is a digital NTSC/PAL encoder. By inputting digital image data conforming to ITU Rec. 656 or ITURBT 601, it outputs selected analog composite video signals, analog S video signals or Y, R-Y, B-Y signals. For the scanning system, interlaced or noninterlaced mode can be selected. Since the MSM7652 is provided with pins dedicated to overlay function, text and graphics can be superimposed on a video signal. In addition, this encoder has an internal 10-bit DAC. So, when compared with using a conventional analog encoder, the number of components, the board space, and points of adjustment can greatly be reduced, thereby realizing a low cost and high-accuracy system. The MSM7652 provides the optional functions such as Closed Caption Signal Generation Function. The host interface provided conforms to Philips's I2C specifications, which reduces interconnections between this encoder and mounting components. The internal synchronization signal generator (SSG) allows the MSM7652 to operate in master mode. FEATURES • Video signal system: NTSC/PAL • Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines) • Input digital level: conforms to ITU-R601 (CCIR601) • Input-output timing: conforms to ITU Rec. 656 or ITURBT 624-4 • Input signal sampling ratio : Y:Cb:Cr = 4:2:2 • Supported input formats · ITU Rec. 656 · YCbCr 27 MHz format (8-bit input) · ITU-R601 13.5 MHz (8-bit (Y) + 8-bit (CbCr) input) • Output video signals · NTSC/PAL composite video signals and S video signals · Y, R-Y, B-Y analog signals (selectable) • Sampling frequency : 27 MHz • Internal SSG circuit (Can operate as a master in other operation modes than CCIR Rec. 656 mode) • Internal 3ch 10-bit DAC • 3-bit title graphics can be displayed • Color bar function • I2C-bus host interface function • 3.3 V single power supply (each I/O pin is 5 V tolerable) • Closed caption function • Package 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSM7652GS-2K) 1 MSM7652 ¡ Semiconductor APPLICATIONS • Video CD • Video game equipment • Electronic still cameras • Video file systems • Video cameras • Videophones • Multimedia equipment • Video printers • Videoconferencing systems • Scanners • Video graphics boards 2 BLOCK DIAGRAM ¡ Semiconductor RESET_L OLC OLR OLG OLB YUV color Generator Y Level converter U Level converter V Level converter Closed Caption Block VSYNC_L HSYNC_L BLANK_L CLKX2 Black & Blank Pedestal Overlay Control Interpolator + LPF Interpolator + LPF IPF DAC YA (Y) YD[7:0] CD[7:0] Prologue Block IPF DAC CVBSO (B-Y) Color Burst Generator Subcarrier Generator IPF DAC CA (R-Y) VREF IPF = Interpolation Filter Sync Generator & Timing Controller I2C Control logic Test Control logic FS COMP SEL[2:1] MS MODE CLKX1O CLKSEL SCL SDA ADRS TENB TEST1 OUTSEL MSM7652 3 MSM7652 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) 52 CVBSO (B-Y) 50 CA (R-Y) 54 YA (Y) 44 TEST1 48 COMP  DVDD MS 1 2 3 4 5 6 7 8 9 SDA SCL ADRS RESET_L MODE OLC OLR OLG 10 OLB 11 CLKX1O 12 OUTSEL 13 DVDD 14 DGND 15 VSYNC_L 16 HSYNC_L 17 BLANK_L 18 YD7 19 YD6 20 NC 21 YD5 22 YD4 23 YD3 24 YD2 25 YD1 26 YD0 27 DGND 28 NC : No-connection pin 56-Pin Plastic QFP 43 DGND 42 DVDD 41 SEL2 40 SEL1 39 CLKSEL 38 CD0 37 CD1 36 CD2 35 CD3 34 CD4 33 CD5 32 CD6 31 CD7 30 CLKX2 29 DVDD 56 DGND 49 AGND 53 AGND 4 45 TENB 46 VREF 55 AVDD 51 AVDD 47 FS ¡ Semiconductor MSM7652 PIN DESCRIPTIONS (1/2) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 I/O I/O I I I/O I I I I I I I I O I I/O Symbol DVDD MS SDA SCL ADRS RESET_L MODE OLC OLR OLG OLB CLKX1O OUTSEL DVDD DGND VSYNC_L HSYNC_L BLANK_L 3.3 V digital power supply Selects between Master and Slave at 27 MHz or 13.5 MHz YCbCr operation. Pulled down I2C interface data bus I2C interface clock bus I2C-bus Slave address setting pin ("0" : 1000100 / "1" : 1000110). Pulled down System reset signal. Negative porality Broadcasting mode select pin. "0" : NTSC/"1" : PAL. Pulled down Transparent control signal. "1" indicates overlay signal. Normally fixed to "0". Overlay text color (Red component). Normally fixed to "0". Overlay text color (Green component). Normally fixed to "0". Overlay text color (Blue component). Normally fixed to "0". 13.5 MHz divided clock output signal Video output signal format select pin. "0" : Y/C & Composite signal, "1" : Y/B-Y/R-Y (component) signal. Pulled down 3.3 V digital power supply Digital GND Vertical sync signal input/output pin (ITU656: O, YCbCr: I/O) Negative polarity Horizontal signal input/output pin (ITU656 : O, YCbCr: I/O) Negative polarity Composite blank signal. Negative polarity. See the description on page 15 for the operating requirement. MSB 2 bits of 8-bit digital image data input pins (for ITU656 and YCbCr 27 MHz). Level conforms to ITU-601. 19, 20 I YD7 to YD6 MSB 2 bits of 8-bit digital image luminance signal input pins (for YCbCr). Level conforms to ITU-601. YD7 is MSB. 21 NC Not connected LSB 6 bits of 8-bit digital image data input pins (for ITU656 and YCbCr 27 MHz). Level conforms to ITU-601. 22 to 27 I YD5 to YD0 LSB 6 bits of 8-bit digital image luminance signal input pins (for YCbCr). Level conforms to ITU-601. YD0 is LSB. 28 29 30 31 to 38 39 I I/O I DGND DVDD CLKX2 CD7 to CD0 CLKSEL Digital GND 3.3 V digital power supply Clock input pin (27 MHz) 8bit digital image chrominance signal data input pins (13.5 MHz mode). Level conforms to ITU-601. Fixed to "0" for ITU Rec. 656, 27 MHz-YCbCr mode. Operation mode select pin. "0" : 27 MHz mode / "1" : 13.5 MHz mode. Description 5 MSM7652 ¡ Semiconductor PIN DESCRIPTIONS (2/2) Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 O O O I I I/O I I I/O I I Symbol SEL1 SEL2 DVDD DGND TEST1 TENB VREF FS COMP AGND CA AVDD CVBSO AGND YA AVDD DGND (See Page 32 for details) Interface select pin. ITU656 : "0", YCbCr 27 MHz : "1" (See Page 32 for details) Pulled down 3.3 V digital power supply Digital GND Input pin1 for testing. Normally fixed to "0". (See Page 32 for details) Pulled down Input pin2 for testing. Normally fixed to "0". Pulled down Reference voltage for DAC DAC full scale adjustment pin. DAC phase complement pin. Analog GND Analog color chrominance signal output pin or component B-Y signal output pin. 3.3 V analog power supply Analog composite signal output pin or component R-Y signal output pin. Analog GND Analog luminance signal output pin or component Y signal output pin. 3.3 V analog power supply Digital GND Description Enable pin. Normally fixed to "0". Sleep mode "1" with TEST1 = "0" 6 ¡ Semiconductor MSM7652 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Analog Output Current Power Consumption Storage Temperature Symbol DVDD AVDD VI IO PW TSTG Condition — — DVDD = 3.3 V — — — Rating –0.3 to +4.5 –0.3 to +4.5 –0.3 to +5.5 50 600 –55 to +150 Unit V V mA mW °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage (*1) "H" Level Input Voltage "L" Level Input Voltage Operating Temperature 1 Operating Temperature 2 External Reference Voltage DA Current Setting Resistance DA Output Load Resistance Symbol DVDD AVDD VIH VIL Ta1 Ta2 Vrefex Riadj RL Condition — — — — DVDD = AVDD = 3.3 V DVDD = AVDD = 3.3 V DA output load = 37.5 W DVDD = AVDD = 3.3 V, Ta = 25˚C (*2) (*3) Min. 3.0 3.0 2.2 — 0 0 — — — Typ. 3.3 3.3 — — 25 25 1.25 385 75 Max. 3.6 3.6 — 0.8 70 65 — — — Unit V V V ˚C ˚C V W W (*1) (*2) (*3) Supply an equal voltage to both DVDD and AVDD. A volume control resistor of approx. 500 W is recommendable for adjusting the output current. When a DA converter analog output is terminated with a 37.5 W load, Riadj = approx. 192 W. Indicates the value when Riadj = 385 W (typical value). 7 MSM7652 ¡ Semiconductor ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V) Parameter "H" Level Output Voltage "L" Level Output Voltage Input Leak Current Output Leak Current Power Supply Current (operating) Power Supply Current (standby) Power Supply Current (Sleep mode) I2 C-bus SDA Output Voltage I2C-bus SDA Output Current Internal Reference Voltage DA Output Load Resistance Integral Linearity Differential Linearity Symbol VOH VOL II IO IDDO IDDS IDDSM SDAVL SDAIO Vrefin RL SINL SDNL Condition IOH = –4 mA (*1) IOL = 4 mA (*1) IOL = 6 mA (*2) VI = GND to DVDD VI = GND to DVDD (*3) — RESET_L = "L" CLKX2 = 0 MHz SEL2 = "H" Low level, IOL = 3 mA During Acknowledge — — — — Min. 0.7VDD — –10 –10 — — 0.03 0 3 — Typ. — — — — 120 60 0.05 — — 1.25 75 ±2 ±1 Max. — 0.4 +10 +10 140 65 0.5 0.4 — — Unit V V mA mA mA mA mA V mA V W LSB LSB (*1) (*2) (*3) VSYNC_L, HSYNC_L, CD[7:0] CLKX1O SDA AC Characteristics (Ta = 0 to 70°C, DVDD = 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V) Parameter CLKX2 Cycle Time Input Data Setup Time Input Data Hold Time Output Delay Time CLKX1O Delay Time I2C-bus Clock Cycle Time I2C-bus High Level Cycle I2C-bus Low Level Cycle Symbol TS ts1 th1 td1 td2 tC_SCL tH_SCL tL_SCL Condition — — — — — Rpull_up = 4.7 kW Rpull_up = 4.7 kW Rpull_up = 4.7 kW Min. — 7 5 5 5 200 100 100 Typ. Max. 36.4 — — — — — — — — — — 25 25 — — — Unit ns ns ns ns ns ns ns ns 8 ¡ Semiconductor INPUT/OUTPUT TIMING Input timing CLKX2 HSYNC_L, VSYNC_L, BLANK_L, YD, CD, MS, MODE, OLR, OLG, OLB, OLC Output timing HSYNC_L, VSYNC_L CLKX1O 
, TS ts1 Invalid data th1 td1 td2 7 8 9 ACK tC_SCL 1 tL_SCL MSM7652 valid data I2C-bus Interface Input/Output Timing The following figure shows I2C-bus basic input/output timing. SDA SCL MSB S Start Condition Data Line Stable: Data Valid Change of Data Allowed 1 2 2 3-8 tH_SCL 9 ACK P Stop Condition I2C-bus Basic Input/Output Timing 9 MSM7652 ¡ Semiconductor BLOCK FUNCTIONAL DESCRIPTION 1. Prologue Block This block separates input data at the ITU Rec.656 format into a luminance signal (Y) and a chrominance signal (Cb & Cr), and also generates information concerning sync signals HSYNC_L, VSYNC_L, and BLANK_L. This block separates input data at the 27 MHz YCbCr (8-bit input) format into a luminance signal (Y) and a chrominance signal (Cb & Cr). This block separates input data at the 13.5 MHz YCbCr (16-bit input) format into a chrominance signal Cb and a chrominance signal Cr. Of the processed input data, luminance and chrominance signals other than valid pixel data are replaced by 8'h10 and 8'h80 respectively. 2. Y Limiter Block This block limits the luminance input signal by clipping the lower limit of an input signal outside the ITU601 Standard • Signals are limited to YD = 16 when YD < 16. • Signals are limited to TD = 254 when YD (input during a valid pixel period) = 255. In other cases, signals are fed as is to next processing. 3. C Limiter Block This block limits the chrominance signal by clipping the upper and lower limits of the input signal outside the ITU601 Standard. CD = 1 when CD = 0 is input during a valid pixel period. CD = 254 when CD = 255 is input during a valid pixel period. • Y Level Converter Converts ITU-601 standard luminance signal level to DAC digital input level. • U Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. • V Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. • YUV Color Generator This block generates luminance and chrominance signals from over lay color signals OLR, OLG and OLB. Control signals (CR [2:0] ) control the output content (overlay or color bar) and output level (100%, 75%, 50%, 25%). • Overlay Control This block selects input image data or YUV Color Generator output signals. It is determined by the level of the control signal (OLC, CR [2]), as shown below: (x : don't care) CR [2] = 1, OLC = x: Selects color bar signal (YUV Color Generator output signal). CR [2] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal). CR [2] = 0, OLC = 0: Selects input image data. 10 ¡ Semiconductor • Black & Blank Pedestal This block adds sync signals at the luminance side to luminance signals. MSM7652 • Interpolator + LPF This block executes data interpolation and the elimination of high frequency components by LPF for input chrominance signals. • I2C Control Logic This is the serial interface block based on I2C standard of Phillips Corporation. Internal registers MR and CR can be set from the master side. When writing to the internal registers other than MR [1] (black level control) and CR [1:0] (overlay level), written contents are immediately set to them. It is during the vertical blanking period that written contents are set to MR [1] and CR [1:0]. • Sync Generator & Timing Controller This block generates sync signals and control signals. This block operates in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. • Color Burst Generator Outputs U and V components of amplitude of burst signals. • Subcarrier Generator Executes color subcarrier generation. • Interpolation Filter (IPF) This block performs upsampling at CLKX2 for luminance signals and chrominance signals modulated with CLKX1 divided from CLKX2. Interpolation processing is executed in this process. • Closed Caption Block This block generates the signal for closed caption. 11 MSM7652 ¡ Semiconductor INPUT DATA FORMAT The signal level specified by the ITU601 is input. When other signal levels than specified by the ITU601 are input, the luminance signal level is clipped to 16 to 254 and the chrominance signal level to 1 to 254. For chrominance signal input, the offset binary and 2's complement formats are available by setting of internal registers. Digital Level 100% White level 235 240(112) Digital Level 128(0) Black Level 16 Y data 16(–112) C data Input luminance signal level Input chrominance signal level Basic Pixel Sampling Ratio 4:2:2 is supported. CLKX1 YD CD Y1 Cb1 Y2 Cr1 Y3 Cb3 Y4 Cr3 Y5 Cb5 Y6 Cr5 4:2:2 sampling at 8bit Y/8bit CbCr input 12 ¡ Semiconductor MSM7652 INPUT TIMING (ITUR656 input) The input data is fed in the encoder at the rising edge of a clock pulse. CLKX2 DATA CLKX1O OLR, OLG, OLB, OLC don't care don't care SAV(1st) SAV(2nd) SAV(3rd) SAV(4th) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th) VALID DATA Input Timing RELATIONSHIP BETWEEN BLANK SIGNAL AND INPUT IMAGE DATA The blank signal is generated by the ITU Rec.656 standard input data. The input image data is valid when the blank signal is "H". 13 MSM7652 ¡ Semiconductor VALID DATA RANGE According to the ITU Rec.656 standard, the pixel data immediately from SAV (4th word) to a fixed value before EVA is valid. The following figure shows the relationship between the input data at the CCIR Rec.656 format and the sync, luminance, chrominance signals which are processed inside the encoder. Note) The values in parenthesis indicate values in PAL mode. 1716Tclkx2 (NTSC)/1728clkx2 (PAL) 1440T (NTSC/PAL) SAV EAV EAV 20Tclkx1 (20Tclkx1) 20Tclkx1 (20Tclkx1) ITU Rec.656 standard input data 4Tclkx2 Sync signal VSYNC_L (0H) generated by input signal Sync signal VSYNC_L (1/2) generated by input signal Sync signal HSYNC_L generated by input data Cb0, Y00, Cr0, Y01, Cb1, Y10, Cr1, Y11.... 11Tclkx1 (4Tclkx1) 4Tclkx2 63Tclkx1 (63Tclkx1) 67Tclkx1 (67Tclkx1) 1/2H 4Tclkx1 (4Tclkx1) 9Tclkx1 (16Tclkx1) Sync signal BLANK_L generated by input data 127Tclkx1 (142Tclkx1) 136Tclkx1 (146Tclkx1) 711Tclkx1 (702Tclkx1) 127Tclkx1 (142Tclkx1) BLANK_L internally generated to assure the horizontal and vertical periods Luminance signal separated from input data Chrominance signal separated from input data 8'h10 8'h80 711Tclkx1 (702Tclkx1) Y00 Y01 Y10 Y11 Cb0 Cr0 Cb1 Cr1 1H 8'h10 8'h80 Composite signal Relationship between input data and sync signal, luminance signal, chrominance signals 14 ¡ Semiconductor MSM7652 CLOCK TIMING2 (8bit Y/8bit CbCr input) Input Data Timing Input data and sync signals are fed into the encoder at the rising edge of CLKX2. Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L. Chrominance signal of input data at this time is regarded as Cb. ACTIVE VIDEO LINE tACT tSTART CLKX2 HSYNC_L YD, CD, OLR, OLB, OLG,OLC BLANK_L ts1 don't care th1 don't care VALID DATA Video data input timing Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the tACT period. When BLANK_L is "H" during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. The values of tSTART differ slightly between in master mode and in slave mode. The values of tSTART are as follows. In YCbCr format input mode, the values of tSTART are the same, in 8 bit (Y) + 8 bit (CbCr) mode or in 8 bit (YCbCr) mode. In master mode Operation mode ITU 601 NTSC ITU 601 PAL tSTA – tS1 = tSTART tSTA(Ts) 250 280 In slave mode Operation mode ITU 601 NTSC ITU 601 PAL tSTA(Ts) 260 290 15 MSM7652 ¡ Semiconductor Timing of Input Data to HSYNC_L CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC YD Invalid Data Invalid Data tSTART Invalid Data Invalid Data Cb0 Y00 Cr0 tACT Y01 Valid Data Cb1 Y10 Input Timing when BLANK_L is Input CLKX2 BLANK_L YD Cb0 Y00 Cr0 Y01 Cb1 Input timing at 27 MHz in YCbCr format Timing of Input Data to HSYNC_L CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC YD CD Invalid Data Invalid Data Invalid Data tSTART Invalid Data Invalid Data Invalid Data Y0 Cb0 tACT Y1 Cr0 Valid Data Y2 Cb1 Input Timing when BLANK_L is Input CLKX2 BLANK_L YD CD Y0 Cb0 Y1 Cr0 Y2 Cb1 Input timing at 13.5 MHz in YCbCr format 16 ¡ Semiconductor MSM7652 Internal Synchronization Output Timing Input and output timing of HSYNC_L and VSYNC_L in master mode is as follows. CLKX2 td1 HSYNC_L VSYNC_L td1 Output timing of internal synchronization, HSYNC_L and VSYNC_L VSYNC_L YA 523 524 525 1 2 3 4 5 6 7 17 18 Output timing of internal synchronization VSYNC_L 17 MSM7652 ¡ Semiconductor OUTPUT FORMAT The timing conforms to the ITU624 standard. In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of internal regsiters. Data level on the DAC input terminal: When the contents of 100% luminance order color bar are input into the encoder, the input level is as follows. DAC data Lumi (IRE) 957 133 Composite Wave Form (NTSC) Yellow White Cyan Green Magenta Red Blue Black 775 715 610 549 450 390 338 285 266 224 114 4 100 89 70 59 41 30 20 11 7.5 0 –20 –40 NTSC Composite Signal (Setup 7.5) 18 ¡ Semiconductor MSM7652 DAC data Lumi (IRE) 775 715 610 549 450 390 285 224 100 89 70 59 41 30 11 0 Y Wave Form (NTSC) White Yellow Cyan Green Magenta Red Blue Black 4 –40 NTSC Y Signal Output (Setup 0) DAC data Lumi (IRE) 858 836 754 622 512 402 270 188 166 63 59 44 20 0 –20 –44 –59 –63 C Wave Form (NTSC) Yellow Cyan Green Magenta Red Blue Color Burst NTSC C Signal Output 19 MSM7652 Composite Wave Form (PAL) Yellow White 973 133 Cyan Green Magenta ¡ Semiconductor DAC data Lumi (IRE) Red Blue Black 792 731 627 566 467 406 359 302 241 123 4 100 89 70 59 41 30 21.5 11 0 –21.5 –43 PAL Composite Signal DAC data Lumi (IRE) 792 731 627 566 467 406 302 241 100 89 70 59 41 30 11 0 Y Wave Form (PAL) White Yellow Cyan Green Magenta Red Blue Black 4 –43 PAL Y Signal Output 20 ¡ Semiconductor MSM7652 DAC data Lumi (IRE) 858 836 754 630 512 394 270 188 166 63 59 44 21.5 0 –21.5 –44 –59 –63 C Wave Form (PAL) Yellow Cyan Green Magenta Red Blue Color Burst PAL C Signal Output 21 MSM7652 ¡ Semiconductor NTSC (Interlaced) Field 1 Reference sub-carrier phase NEGATIVE HALF CYCLE Burst relative –180° to B-Y axis POSITIVE HALF CYCLE Burst relative 180° to B-Y axis 259 260 261 A 262 263 1 2 B D 3 4 5 C 6 7 8 17 18 19 E Field 2 Reference sub-carrier phase 259 260 261 A 262 263 1 2 B D 3 4 5 C 6 7 8 17 18 19 E Field 3 Reference sub-carrier phase 259 260 261 A 262 263 1 2 B D 3 4 5 C 6 7 8 17 18 19 E Field 4 Reference sub-carrier phase 259 260 261 A 262 263 1 2 B D 3 4 5 C 6 7 8 17 18 19 E Output timing (Interlaced NTSC) 22 ¡ Semiconductor MSM7652 Symbol A B C D E Name First equalizing pulse period (3H) Vertical synchronization period (3H) Second equalizing pulse period (3H) Burst pause period Vertical blanking period (20H) Period Odd field (Even field) 259.5 to 262.5H 1 to 3H 4 to 6H 1 to 6,259.5 to 262.5H 1 to 17,259.5 to 262.5H Output timing (Interlaced NTSC) 23 MSM7652 ¡ Semiconductor NTSC (Non-interlaced) NEGATIVE HALF CYCLE Burst relative –180° to B-Y axis Reference sub-carrier phase POSITIVE HALF CYCLE Burst relative 180° to B-Y axis Continuous Odd Field 260 261 A 262 1 2 B D 3 4 5 C E 6 7 8 17 18 19 Reference sub-carrier phase 260 261 A 262 1 2 B D 3 4 5 C E 6 7 8 17 18 19 Continuous Even Field Reference sub-carrier phase 260 261 A 262 1 2 B D 3 4 5 C E 6 7 8 17 18 19 Reference sub-carrier phase 260 261 A 262 1 2 B D 3 4 5 C E 6 7 8 17 18 19 Output timing (Non-interlaced NTSC) Period Continuous odd • even field 261 to 262H 1 to 3H 4 to 6H 261 to 6H 261 to 17H Symbol A B C D E Name First equalizing pulse period (2H) Vertical synchronization period (3H) Second equalizing pulse period (2H) Burst pause period Vertical blanking period (19H) Output timing (Non-interlaced NTSC) 24 ¡ Semiconductor MSM7652 PAL (Interlaced) Field 1,5 Burst phase +135° +V Burst phase -135° -V 309 310 311 312 313 A 1 B 2 3 4 C 5 6 7 8 23 24 25 D E Field 2,6 309 310 311 312 313 A 1 B D 2 3 4 C E 5 6 7 8 23 24 25 Field 3,7 309 310 311 312 313 A 1 B D 2 3 4 C E 5 6 7 8 23 24 25 Field 4,8 309 310 311 312 313 A 1 B 2 3 4 C 5 6 7 8 23 24 25 D E Output timing (Interlaced PAL) Symbol A B C D E Name Field 1,5 First equalizing pulse period (2.5H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (25H) 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6,310 to 312.5H 1 to 22.5,311 to 312.5H Field 2,6 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5.5,308.5 to 312.5H 1 to 22.5,311 to 312.5H Period Field 3,7 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5,311 to 312.5H 1 to 22.5,311 to 312.5H Field 4,8 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6.5,309.5 to 312.5H 1 to 22.5,311 to 312.5H Output timing (Interlaced PAL) 25 MSM7652 ¡ Semiconductor PAL (Non-interlaced) Burst phase +135° +V Burst phase -135° -V Continuous Odd Field 309 310 311 A 312 1 B 2 3 4 C 5 6 7 8 23 24 25 D E 309 310 311 A 312 1 B 2 3 4 C 5 6 7 8 23 24 25 D E Continuous Even Field 309 310 311 A 312 1 B 2 3 4 C 5 6 7 8 23 24 25 D E 309 310 311 A 312 1 B 2 3 4 C 5 6 7 8 23 24 25 D E Output timing (Non-interlaced PAL) Period Continuous odd • even field 311 to 312H 1 to 2.5H 2.5 to 5H 311 to 6H 311 to 22H Symbol A B C D E Name First equalizing pulse period (2H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (24H) Output timing (Non-interlaced PAL) 26 ¡ Semiconductor q w e r q 1/2H w 1/2H e MSM7652 Setting content of equalizing pulse vertical synchronization period (Ts is sampling clock cycle in each mode) q ITU 601 NTSC ITU 601 PAL w e 1/2H 31Ts 365Ts 64Ts 429Ts 32Ts 369Ts 63Ts 432Ts qEqualizing pulse width qBlanking level wVertical sync pulse width w(synchronizing + blanking level) ¥ (2/3) e(synchronizing + blanking level) ¥ (1/3) eSerration rSynchronzing level 1H r e w q t q e r w t qHorizontal sync pulse width wBurst signal output period eBurst signal start rHorizontal blanking period (excluding front porch) tFront porch start qSynchronzing level w(synchronizing + blanking level) ¥ (1/3) e(synchronizing + blanking level) ¥ (2/3) rBlanking level tPeak to peak value of burst Horizontal blanking period Setting content of horizontal blanking period (Ts is sampling clock cycle in each mode) q ITU601 NTSC ITU601 PAL 63Ts 63Ts w 31Ts 31Ts e r t Total dots/1H 858 864 71Ts 127Ts 838Ts 75Ts 142Ts 844Ts Setting content of horizontal blanking period 27 MSM7652 ¡ Semiconductor Setup Level Setting When the NTSC operation mode is selected, one of the two kinds of setup level can be selected by setting of registers. When the setup level 0 is selected, the Black-to-White is 100IRE. When the setup level 7.5IRE is selected, the Black-to-White is 92.5IRE. However, this setup function is valid only for the NTSC mode and invalid for the PAL mode. Color Bar Generation Function The 75% luminance order color bar or 100% luminance order color bar is output by setting internal registers. The output timings for each color bar color is as follows. White Yellow Cyan Green Magenta Red Blue Black q w e r t y u Output timing of each color bar color Operation mode ITU601 NTSC ITU601 PAL (Ts : sampling block period) hblank 127Ts 142Ts q 216Ts 230Ts w 305Ts 318Ts e 394Ts 406Ts r 483Ts 494Ts t 572Ts 582Ts y 661Ts 670Ts u 750Ts 757Ts 1H 858Ts 864Ts Contents of color bar output timing setting 28 ¡ Semiconductor MSM7652 I2C BUS FORMAT Basic input format of I2C-bus interface is shown below. S Slave Address A Subaddress A Data 0 A ..... Data n A P Symbol S Slave Address A Subaddress Data n P Start condition Description Slave address 1000100X (ADRS pin : 0) or 1000110X (ADRS pin : 1), the 8th bit is R (1)/W (0) signal. Acknowledge. Generated by slave Subaddress byte Data byte and acknowledge continues until data byte stop condition is met. Stop condition As described above, it is possible to read and write data from subaddress to subaddress continuously. Reading from and writing to discontinuous addresses is performed by repeating the Acknowledge and Stop condition formats after Data 0. If one of the following matters occurs, the encoder will not return "A" (Acknowledge). • The slave address does not match. • A non-existent subaddress is specified. • The read/write attribute of a register does not match "X" (read : 1/write : 0 control bit). The input timing is shown below. SDA SCL MSB S Start Condition Data Line Stable: Data Valid Change of Data Allowed 1 2 7 8 9 ACK tC_SCL 1 tL_SCL 2 3-8 tH_SCL 9 ACK P Stop Condition I2C-bus Basic Input/Output Timing 29 MSM7652 ¡ Semiconductor CLOSED CAPTION FUNCTION The closed caption function based on the NCI standard is available. The caption information on each line is multiplexed as a 26-cycle signal which is synchronized at 503 kHz. Each cycle is described below. Cycles 1 to 7 Cycles 8 to 10 Cycles 11 to 26 Clock-Run-in period Start Code Caption Information 7-cycle clock signal to synchronize caption data with caption information. Fixed signal with logical level "001" 2-byte multiplex information with combination of the ASCII code bits 0 - 6 and the 7ODD parity bit. The first byte is multiplexed in cycles 11 to 18 and the second byte is multiplexed in cycles 19 to 26, starting from LSB. The output timing when data is multiplexed by the closed caption function is shown below. 50IRE Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 50IRE Transition time 20IRE 0IRE –40IRE Clock Run in 13.9 ms (reference) 10.0 ms (reference) Start Code 6.0 ms (reference) 16-bit Information 31.8 ms (reference) 61.7 ms (reference) Caption signal 100% 50% Transition time : ns Transition time 30 ¡ Semiconductor MSM7652 INTERNAL REGISTERS The register (ID number) for the Anticopy function and the register (CCSTAT) for the closed caption can be read. The registers other than ID number can be written. Details of the internal registers are described below. (Values marked * are set by default.) Sub- Default Register name R/W address value MR (Mode register) Write Only 00 00 MR[4] Override Switching between the external terminal and internal register settings (for the operation mode) *0 : External terminal setting enabled 1 : Internal register setting enabled MR[3] Chroma format Chrominance signal input format *0 : Offset binary 1 : 2's complement MR[2] Black level control Black level setup Note : Valid in NTSC mode only *0 : Black level 0IRE 1 : Black level 7.5IRE MR[1] Master/Slave Master or slave operation select *0 : Slave 1 : Master MR[0] Video mode select Operation mode switching *0 : ITU601 NTSC 1 : ITU601 PAL CR (Command Register) Write Only 01 03 CR[4] CR[3] Undefined Interlace — Scanning method *0 : Interlace 1 : Non-interlace CR[2] Color bar Adjusting luminance order color bar output control *0 : Input image data or overlay data 1 : Luminance order color bar CR[1:0] Overlay level Overlay signal/adjusting luminance order color bar output level control 00 : 25% 01 : 50% 10 : 75% *11 : 100% Item to be set Description 31 MSM7652 ¡ Semiconductor Sub- Default Register name R/W address value CCEN Write Only 02 00 CCEN[0] Closed Caption Enable Closed caption function on/off control *0 : C.C. encoding off 1 : Odd field encoding on 2 : Even field encoding on 3 : Both field encoding on CCLN Write Only 03 11 CCLN[4:0] Closed Caption Line Number Closed caption data insertion line number setting NTSC : CCLN + 4 PAL : CCLN + 1 CCODT0 Write Only CCODT1 Write Only CCEDT0 Write Only CCEDT1 Write Only CCSTAT Read/ Write 08 00 CCSTAT[0] Odd field C.C. status 07 00 CCEDT1[7:0] 2nd byte of C.C. data, EVEN field 06 00 CCEDT0[7:0] 1st byte of C.C. data, EVEN field 05 00 CCODT1[7:0] 2nd byte of C.C. data, ODD field 04 00 CCODT0[7:0] 1st byte of C.C. data, ODD field First byte closed caption data in odd-number field Second byte closed caption data in odd-number field First byte closed caption data in even-number field Second byte closed caption data in even-number field odd-number field status *0 : CCODT0, CCODT1 writing completed 1 : ODD Field C.C. bytes ENCODE completed CCSTAT[1] Odd field C.C. status Even-number field status *0 : CCEDT0, CCEDT1 writing completed 1 : EVEN Field C.C. bytes ENCODE completed Item to be set Description OPERATION MODE SETTING BY PIN CONTROL The contents of control using TEST1, SEL1, SEL2, CLKSEL, and MS are shown below. TEST1 SEL1 SEL2 CLKSEL MS TEST1 0 0 0 0 0 0 0 : Normal operation 0 : Normal operation 0 : ITU Rec. 656 0 : 27 MHz 0 : Slave SEL1 0 0 0 0 0 1 SEL2 0 0 0 1 1 x 1 : Test mode 1 : Sleep mode 1 : Y Cb Cr 1 : 13.5 MHz 1 : Master Operation mode ITUR656 Slave 13.5 MHz YCbCr Slave 13.5 MHz YCbCr Master 27 MHz YCbCr Slave 27 MHz YcbCr Master Sleep Mode CLKSEL MS 0 0 1 0 1 1 0 0 0 1 x x x : don't care 32 ¡ Semiconductor MSM7652 FILTER CHARACTERISTICS The characteristics of LPF used for color signal processing and interpolation filters used for upsampling processing are shown below. LPF for 422 color signals The following shows the characteristics when the clock frequency is 13.5 MHz. 0 –20 Level [dB] –40 –60 –80 –100 0 1 2 3 4 Frequency [MHz] 5 6 7 422 Interpolation + LPF Frequency Characteristic Interpolation The following shows the characteristics when the clock frequency is 27 MHz. 0 –20 Level [dB] –40 –60 –80 –100 0 2 4 6 8 Frequency [MHz] 10 12 14 Up Sampling Filter Frequency Characteristic (Note) The characteristics of these filters are based on design data. 33 MSM7652 ¡ Semiconductor APPLICATION CIRCUIT EXAMPLE 5 V or 3.3 V RL 5 V or 3.3 V I2C Controller RL 3.3 V 3.3 V MS MODE OUTSEL CLKSEL SEL1 SEL2 OLR OLG OLB OLC DVDD AVDD SDA SCL DIP SW VREF Typ. 1.25 V 3.3 V RC CC = 0.1 µF FS COMP LPF YA MSM7652 R1 LPF CVBSO R1 LPF AMP CA R1 DGND AGND CLKX2 RC = 500 Ω VR AMP AMP Overlay Controller YD[7:0] CD[7:0] YD[7:0] CD[7:0] CLKX1O VSYNC_L HSYNC_L BLANK_L Recommended Analog Output Circuit +AVCC 0.1 mF 3.6 mH 150 W 164 pF 164 pF 150 W + – 75 W 560 W YA CA CVBSO 1000 mF + OUTPUT 560 W 0.1 mF LPF (Toko-make 621LJN-1471 is recommended.) –AVCC Note: The termination of a DA converter analog output with a 37.5 W load eliminates need for an AMP. 34 ¡ Semiconductor MSM7652 PACKAGE DIMENSIONS (Unit : mm) 56-Pin Plastic QFP 35 MSM7652 ¡ Semiconductor NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, and medical equipment including life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 2. 3. 4. 5. 6. 7. 8. Copyright 1998 Oki Electric Industry Co., Ltd. 36