MSM7717-02

E2U0041-28-81 ¡ Semiconductor MSM7717-01/02/03 ¡ Semiconductor Single Rail CODEC This version: Aug. 1998 MSM7717-01/02/03 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400 Hz with filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for ISDN terminals and telephone terminals in digital wireless systems. The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B. The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver differentially. FEATURES • Single power supply: 2.7 V to 3.8 V • Low power consumption Operating mode: 20 mW Typ. VDD = 3 V Power-down mode: 0.03 mW Typ. VDD = 3 V • Conforms to ITU-T Companding law MSM7717-01: m/A-law pin selectable MSM7717-02: m-law MSM7717-03: A-law • Built-in PLL eliminates a master clock • Serial data rate: 64/128/256/512/1024 kHz 96/192/384/768/1536/1544/2048/200 kHz • Adjustable transmit gain • Adjustable receive gain • Built-in reference voltage supply • Package options: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM7717-01GS-K) (Product name: MSM7717-02GS-K) (Product name: MSM7717-03GS-K) 20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K) (Product name: MSM7717-02MS-K) (Product name: MSM7717-03MS-K) 1/19 ¡ Semiconductor MSM7717-01/02/03 BLOCK DIAGRAM AIN– AIN+ GSX – + RC LPF 8th BPF AD CONV. AUTO ZERO PCMOUT TCONT PLL XSYNC BCLK SGC SG SG GEN VR GEN RTIM RSYNC (ALAW) VFRO PWI AOUT– – + SG 5th LPF DA CONV. RCONT PCMIN – + – + SG PWD PWD Logic AOUT+ SG PDN VDD AG DG 2/19 ¡ Semiconductor MSM7717-01/02/03 PIN CONFIGURATION (TOP VIEW) SG 1 AOUT+ 2 AOUT– 3 NC 4 PWI 5 VFRO 6 NC 7 VDD 8 DG 9 PDN 10 RSYNC 11 PCMIN 12   24 SGC SG 1 20 SGC 23 AIN+ 22 AIN– 21 GSX 20 NC AOUT+ 2 AOUT– 3 PWI 4 19 AIN+ 18 AIN– 17 GSX 16 NC VFRO 5 VDD 6 DG 7 19 NC 15 (ALAW)* 14 AG 18 (ALAW)* 17 NC PDN 8 13 BCLK 16 AG RSYNC 9 12 XSYNC 15 BCLK PCMIN 10 11 PCMOUT 14 XSYNC 13 PCMOUT NC : No connect pin 20-Pin Plastic SSOP NC : No connect pin 24-Pin Plastic SOP * The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K. 3/19 ¡ Semiconductor MSM7717-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp. The level adjustment should be performed in any method shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down modes, the GSX output is at AG voltage. 1) Inverting input type C1 Analog input R1 GSX AIN– AIN+ SG R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F) Gain = R2/R1 < 10 R2 – + 2) Noninverting input type C2 Analog input R5 R4 R3 AIN+ AIN– GSX SG + – R3 > 20 kW R4 > 20 kW R5 > 50 kW C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) (F) Gain = 1 + R4 / R3 £ 10 AG Analog signal ground. VFRO Receive filter output. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more. For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO and PWI. During power-saving mode this output is in a high impedance state, and during power-down mode, the VFRO output is at an SG level. When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency Characteristics Adjustment Circuit. 4/19 ¡ Semiconductor PWI, AOUT+, AOUT– MSM7717-01/02/03 PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted with respect to the output of AOUT–. Since these outputs provide differential drive of an impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being activated during the power-saving mode, the amplifiers can output other external signals from AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during the power-down mode. VI R6 R7 Gain = VO/VI = R7/R6 £ 1 Analog output VO ZL SG – + AOUT+ Analog inverted output ZL > 1.2 kW R6 > 20 kW External Signal Input Receive filter – + VFRO PWI AOUT– SG VDD Power supply for 2.7 V to 3.8 V. (Typically 3.0 V) PCMIN PCM data input. A serial PCM data input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The data rate of PCM is equal to the frequency of the BCLK signal. PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLK Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive driver amplifiers are in the operating mode and the other circuits are in the non-operating mode. 5/19 ¡ Semiconductor RSYNC MSM7717-01/02/03 Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz ± 2 kHz, but the electrical characteristics in this specification are not guaranteed. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device operates in the range of 8 kHz ± 2 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. 6/19 ¡ Semiconductor DG MSM7717-01/02/03 Ground for the digital signal circuits. This ground is separate from the analog signal ground AG. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground AG. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from MSD in a sequential order. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down mode. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7717-03 (A-law) outputs the character signal, inverting the even bits. PCMIN/PCMOUT MSM7717-02 (m-law) MSD 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 MSM7717-03 (A-law) MSD 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 Input/Output Level +Full scale +0 –0 –Full scale 7/19 ¡ Semiconductor SG MSM7717-01/02/03 Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is ±200 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power-saving or power-down mode. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the MSM7717-01GS-K/7717-01MS-K has this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will has this pin operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally pulled down. 8/19 ¡ Semiconductor MSM7717-01/02/03 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition — — — — Rating –0.3 to +7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V °C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time High Level Sync Pulse Width Low Level Sync Pulse Width PCMIN Setup Time PCMIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width Symbol VDD Ta VAIN VIH VIL FC FS DC tlr tlf tXS tSX tRS tSR tWSH tWSL tDS tDH RDL CDL Voff — Condition Voltage must be fixed — Connect AIN– and GSX XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW BCLK XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW BCLKÆXSYNC, See Fig. 1 XSYNCÆBCLK, See Fig. 1 BCLKÆRSYNC, See Fig. 1 RSYNCÆBCLK, See Fig. 1 XSYNC, RSYNC, See Fig. 1 XSYNC, RSYNC, See Fig. 1 See Timing Diagram See Timing Diagram Pull-up resistor — Transmit gain stage, Gain = 1 Transmit gain stage, Gain = 10 XSYNC, RSYNC, BCLK Min. 2.7 –30 — 0.45¥VDD 0 Typ. 3.0 +25 — — — Max. 3.8 +85 1.4 VDD 0.16¥VDD Unit V °C VPP V V kHz kHz % ns ns ns ns ns ns ms ms ns ns kW pF mV mV ns 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 6.0 40 — — 100 100 100 100 1 BCLK 1 BCLK 100 100 0.5 — –100 –10 — 8.0 50 — — — — — — — — — — — — — — — 10 60 50 50 — — — — — — — — — 100 +100 +10 1000 9/19 ¡ Semiconductor MSM7717-01/02/03 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIL VOL IO CIN No signal Condition Operating mode VDD = 3.8 V VDD = 3.0 V (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Min. — — — — 0.45¥VDD 0.0 — — 0.0 — — Typ. 10 6.5 2.0 0.005 — — — — 0.2 — 5 Max. 14 10.0 8.0 0.05 VDD 0.16¥VDD 2.0 0.5 0.4 10 — Unit mA mA mA V V mA mA V mA pF Power-saving mode, PDN = 1, BCLK or XSYNC Æ OFF Power-down mode, PDN = 0, BCLK OFF XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW — — Pull-up resistor > 500 W — — 10/19 ¡ Semiconductor Transmit Analog Interface Characteristics MSM7717-01/02/03 (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Input Resistance Output Load Resistance Symbol RINX RLGX CLGX VOGX VOSGX Condition AIN+, AIN– GSX with respect to SG Min. 10 20 — –0.7 Typ. — — — — — Max. — — 30 +0.7 +20 Unit MW kW pF V mV Output Load Capacitance Output Amplitude Offset Voltage Gain = 1 –20 Receive Analog Interface Characteristics (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Input Resistance Output Load Resistance Symbol RINPW PWI RLVF RLAO CLVF CLAO VOVF Output Amplitude VOAO VFRO with respect to SG AOUT+, AOUT– (each) with respect to SG VFRO AOUT+, AOUT– VFRO, RL = 20 kW with respect to SG AOUT+, AOUT–, RL = 0.6 kW with respect to SG AOUT+, AOUT–, Gain = 1 with respect to SG Condition Min. 10 20 0.6 — — –1.0 –1.0 –100 –100 Typ. — — — — — — — — — Max. — — — 30 50 +1.0 +1.0 +100 +100 Unit MW kW kW pF pF V V mV mV Output Load Capacitance VOSVF VFRO with respect to SG Offset Voltage VOSAO 11/19 ¡ Semiconductor AC Characteristics Parameter Symbol Loss T1 Loss T2 Transmit Frequency Response Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Receive Frequency Response Loss R3 Loss R4 Loss R5 SD T1 SD T2 SD T3 Transmit Signal to Distortion Ratio SD T4 SD T5 SD R1 SD R2 SD R3 Receive Signal to Distortion Ratio SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 –30 –40 –45 3 0 –30 –40 –45 3 –10 –40 –50 –55 3 –10 –40 –50 –55 –0.3 –0.6 –1.2 –0.3 –0.6 –1.2 –0.3 *1 *2 *2 *1 0 –0.15 –0.15 0 35 35 35 28 23 36 36 36 30 29 25 24 –0.3 0 MSM7717-01/02/03 (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Level Condition (dBm0) Min. 20 –0.15 –0.15 –0.15 0 –0.15 Typ. 26 +0.07 Reference –0.01 +0.15 0.4 –0.03 Reference –0.02 +0.15 0.56 43 41 38 30 25 43 41 40 33.5 32 30 27 +0.01 Reference 0 –0.03 +0.15 –0.06 Reference –0.02 –0.02 –0.27 +0.3 +0.6 +1.2 dB +0.3 +0.6 +1.2 +0.3 dB +0.2 +0.25 0.8 — — — — — — — — — — +0.3 dB dB dB +0.2 +0.2 0.8 +0.2 Max. — +0.2 dB Unit *1 Psophometric filter is used. *2 Upper columns are specified for the m-law, lower for the A-law. 12/19 ¡ Semiconductor AC Characteristics (Continued) Parameter Symbol Nidle T Nidle R AV T Absolute Level (Initial Difference) AV R AV Tt AV Rt 1020 0 Freq. (Hz) — — MSM7717-01/02/03 (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Level Condition (dBm0) AIN = SG — *1 — *1 *3 VDD = 3.0 V Ta = 25°C *4 VDD = 2.7 V to 3.8 V Ta = –30 to 85°C *4 A to A 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 1020 0 TRANS Æ RECV RECV Æ TRANS Min. — *2 — 0.338 0.483 –0.2 –0.2 Typ. –72.5 –70.5 –76.5 0.35 0.5 — — Max. –68 –74 0.362 Unit Idle Channel Noise dBm0p Vrms 0.518 +0.2 +0.2 dB dB Absolute Level (Deviation of Temperature and Power) Absolute Delay Td tGD T1 tGD T2 0 BCLK = 64 kHz — — — — 0.19 0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 80 76 0.6 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 — — ms Transmit Group Delay tGD T3 tGD T4 tGD T5 tGD R1 tGD R2 0 *5 — — — — — ms Receive Group Delay tGD R3 tGD R4 tGD R5 CR T CR R 0 *5 — — — 75 70 ms Crosstalk Attenuation dB *1 *2 *3 *4 *5 Psophometric filter is used. Upper column is specified for the m-law, lower for the A-law. Input "0" code to PCMIN. AVR is defined at VFRO output. With respect to minimum value of the group delay distortion 13/19 ¡ Semiconductor AC Characteristics (Continued) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Symbol MSM7717-01/02/03 (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Min. 30 — — — 20 CL = 100 pF + 1 LSTTL 20 20 20 Typ. 32 –37.5 –52 30 — — — — Max. — –35 –35 — 200 200 200 200 ns Unit dB dBm0 dBm0 dB Freq. Level Condition (Hz) (dBm0) 0 to 4.6 kHz to DIS 0 4000 Hz 72 kHz S 300 to 3400 fa = 470 fd = 320 0 to 50 kHz 0 –4 50 mVPP 4.6 kHz to 100 kHz 2fa – fd *6 IMD PSR T PSR R tSD tXD1 tXD2 tXD3 Digital Output Delay Time *6 Measured under idle channel noise. 14/19 ¡ Semiconductor TIMING DIAGRAM PCM Data Input/Output Timing Transmit Timing BCLK XSYNC PCMOUT Receive Timing BCLK RSYNC PCMIN
,
, 1 2 3 tXS tSX tWSH tXD1 tSD tXD2 MSD D2 D3 1 2 3 tRS tSR tWSH MSD tDS D2 D3 MSM7717-01/02/03 4 5 6 7 tWSL 8 9 10 D4 D5 D6 D7 tXD3 D8 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. 4 5 6 7 tWSL 8 9 10 tDH D4 D5 D6 D7 D8 Figure 1 Basic Timing 15/19 ¡ Semiconductor MSM7717-01/02/03 APPLICATION CIRCUIT +3 V MSM7717-01 AIN– 0.1 mF GSX AIN+ SG Analog inverted output* Analog output* AOUT+ ALAW AOUT– PWI VFRO 51 kW SGC 10 mF 0V +3 V + 51 kW Analog input PCMOUT XSYNC RSYNC BCLK PCMIN PCM signal output 8 kHz SYNC signal input PCM shift clock input PCM data Control of companding law 1: A-law 0: m-law PDN 0.1 mF AG 1 mF VDD DG Power down control input 1: Normal operation 0: Power down 0 to 10 W * These output signals have amplitudes above and below the offset level of VDD/2. FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT MSM7717-XX R1 AIN– C2 R2 GSX AIN+ SG AOUT+ R5 C4 R4 AOUT– PWI VFRO R3 C3 Receive frequency characteristic Adjustment determined by C3, C4, R3 and R4 Microphone amp M C1 Transmit frequency characteristic Adjustment determined by C1, C2, R1 and R2 16/19 ¡ Semiconductor MSM7717-01/02/03 NOTES ON USE • To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance. • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. • Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. 17/19 ¡ Semiconductor MSM7717-01/02/03 PACKAGE DIMENSIONS (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor MSM7717-01/02/03 (Unit : mm) SSOP20-P-250-0.95-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.18 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19