MSM80C51F

E2E1037-19-41 ¡ Semiconductor MSM80C31F/MSM80C51F ¡ Semiconductor CMOS 8-Bit Microcontroller This version: Mar. 1995 MSM80C31F/80C51F GENERAL DESCRIPTION The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The device includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt structure, a full duplex serial port, and an oscillator and clock circuitry. In addition, the device has two software selectable modes for further power reduction — Idle and Power Down. Idle mode freezes the CPU's in-struction execution while maintaining RAM and allowing the timers, serial port and interrupt system to continue functions. Power Down mode saves the RAM contents but freezes the oscillator causing all other device functions to be inoperative. FEATURES • Low power consumption by 2 mm silicon gate CMOS process technology • Fully static circuit • Internal program memory : 4K bytes (MSM80C51F) • External program memory space : 64K bytes • Internal data memory (RAM) : 128 bytes • External data memory (RAM) space : 64K bytes • I/O ports : 8-bit ¥ 4 ports • Two 16-bit timer/counters • Multifunctional serial port (UART) • Five interrupt sources (Priority can be set) • Four sets of working registers (R0-7 ¥ 4) • Stack : Internal data memory (RAM) 128-byte area can be used arbitrarily (by SP specified) • Two CPU power-down modes (1) Idle mode : CPU stopped while oscillation continued. (Software setting) (2) PD mode : CPU and oscillation all stopped. (Software setting) (Setting I/O ports to floating status possible) • Operating temperature : –40 to +85°C (@ 12 MHz, VCC = 5 V ± 20%) –20 to +70°C (@ 16 MHz, VCC = 5 V ± 5%) • 2-byte 1-machine cycle instructions : 1 msec. @ 12 MHz 0.75 msec. @ 16 MHz • Multiplication/division instructions : 4 msec. @ 12 MHz 3 msec. @ 16 MHz • Instruction code addressing method Byte specification : Data addressing (direct) Bit specification : Bit addressing 1/38 ¡ Semiconductor • Package options 40-pin plastic DIP (DIP40-P-600-2.54) : 44-pin plastic QFP (QFP44-P-910-0.80-2K) : 44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27) : MSM80C31F/80C51F (MSM80C31F-¥¥¥RS) (MSM80C51F-¥¥¥RS) (MSM80C31F-¥¥¥GS) (MSM80C51F-¥¥¥GS) (MSM80C31F-¥¥¥JS) (MSM80C51F-¥¥¥JS) ¥¥¥ indicates the code number. DIFFERENCES BETWEEN MSM80C31F/MSM80C51F AND MSM80C31/MSM80C51 • Operating frequency 0.5 to 16 MHz ..................... MSM80C31F-1/MSM80C51F-1 0.5 to 12 MHz ..................... MSM80C31/MSM80C51/MSM80C31F/MSM80C51F • External clock input terminal XTAL1 ................................. MSM80C31F(-1)/MSM80C51F(-1) XTAL2 ................................. MSM80C31/MSM80C51 • Emulation mode Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in MSM80C31F/MSM80C51F. Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for above three differences are the same as those of MSM80C31/MSM80C51. 2/38 ¡ Semiconductor BLOCK DIAGRAM CONTROL SIGNALS R/W SIGNALS PORT 2 P2.0 to P2.7 ROM 4096 WORDS ¥ 8 BITS PLA SPECIAL FUNCTION REGISTER ADDRESS DECODER ADDRESS DECODER PCHL PORT 0 P0.0 to P0.7 PCLL PCH XTAL1 PCON XTAL2 ALE PSEN EA RESET SP OSC AND TIMING PORT 1 PCL SENSE AMP IR AIR C-ROM DPH DPL R/W AMP ADDRESS DECODER ACC TR2 TR1 128 WORDS ¥ 8 BITS RAMDP PSW ALU BR P1.0 to P1.7 MSM80C31F/80C51F TH1 PORT 3 P3.0 to P3.7 TL1 TH0 TIMER/COUNTER TL0 TMOD TCON IE INTERRUPT IP SBUF(T) SBUF(R) SERIAL IO SCON 3/38 Basic Timing Chart CLOCK WAVEFORMS ¡ Semiconductor CYCLE STEP XTAL1 ALE PSEN RD/WR PORT-0 1 0 1 0 1 0 1 0 S1 S2 S3 M1 S4 S5 S6 S1 S2 S3 M1 S4 S5 S6 S1 S2 S3 M2 S4 S5 S6 S1 S2 S3 M1 S4 S5 S6 DPL&Rr 1 0 1 0 PCL PCH PCH PCL PCH DATA STABLE ,,, ,,, ,,, , ,,, ,, PCL PCH ,,, ,, ACC & RAM DPH & PORT DATA ,,, ,,, PCL PCH ,,, PCL PCH PCL PCH PORT-2 ,,, ,, DATA STABLE ,,, , ,,, ,,, ,, CPU¨PORT PORT¨CPU 1 0 1 0 ,,, ,, , ,, PORT OLD DATA Instruction decoding Instruction execution PC+1 TM+1 PC+1 Port output/input Instruction execution ,, ,, ,,, ,,, ,, ,, ,,, ,, ,,, ,, ,,, ,, ,,, ,, ,,, ,,, , ,,, ,,, ,,, ,,, ,,, Instruction decoding Instruction execution PC+1 TM+1 TM+1 ,,, ,,, External data memory instruction execution Port output/input Instruction execution ,,, ,,, , ,,, ,,, PORT NEW DATA ,,, ,,, ,,, ,,, ,,, ,,, ,, ,, , Instruction decoding Instruction execution PC+1 TM+1 PC+1 , MSM80C31F/80C51F 4/38 ¡ Semiconductor MSM80C31F/80C51F PIN CONFIGURATION (TOP VIEW) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 RXD/P3.0 10 TXD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 40-Pin Plastic DIP 5/38 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) (continued) P1.5 P1.6 P1.7 RESET P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 10 P3.5/T1/HPDI 11
, 44 P1.4 43 P1.3 42 P1.2 41 P1.1 40 P1.0 39 NC 1 2 3 4 5 6 7 8 9 MSM80C31F/80C51F 37 P0.0 36 P0.1 35 P0.2 34 P0.3 33 P0.4 32 P0.5 31 P0.6 30 P0.7 29 EA 28 NC 27 ALE 26 PSEN 25 P2.7 24 P2.6 23 P2.5 P3.6/WR 12 P3.7/RD 13 XTAL2 14 XTAL1 15 VSS 16 VSS 17 P2.0 18 38 VCC P2.1 19 P2.2 20 P2.3 21 44-Pin Plastic QFP P2.4 22 6/38 ¡ Semiconductor MSM80C31F/80C51F PIN CONFIGURATION (TOP VIEW) (continued) 32 PSEN 39 P0.4 38 P0.5 37 P0.6 36 P0.7 31 P2.7 30 P2.6 P0.3 40 P0.2 41 P0.1 42 P0.0 43 VCC 44 NC 1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 29 P2.5 33 ALE 34 NC 35 EA  RESET 10 P3.0/RXD 11 NC 12 P3.1/TXD 13 P1.5 7 P1.6 8 P1.7 9 28 P2.4 27 P2.3 26 P2.2 25 P2.1 24 P2.0 23 NC 22 VSS 21 XTAL1 20 XTAL2 19 P3.7/RD 18 P3.6/WR P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 44-Pin Plastic QFJ (PLCC) P3.5/T1 17 7/38 ¡ Semiconductor MSM80C31F/80C51F PIN DESCRIPTION Symbol VSS VCC Port 0.0 - 0.7 Port 1.0 - 1.7 Port 2.0 - 2.7 Port 3.0 - 3.7 Ground potential Supply voltage during Normal, Idle and Power Down operation Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the mutiplexed low-order address and data bus during accesses to external memory. Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. It can drive CMOS inputs without external pull-ups. Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. It outputs the high-order address byte during accesses to external memory. It can drive CMOS inputs without external pull-ups. Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. It also provides various special features, as shown below: Alternate Function Port Pin (serial input port) RXD P3.0 (serial output port) TXD P3.1 (external interrupt) INT0 P3.2 (external interrupt) INT1 P3.3 (Timer 0 external input) T0 P3.4 (Timer 1 external input) T1 P3.5 (external data memory write strobe) WR P3.6 (external data memory read strobe) RD P3.7 Port 3 can drive CMOS inputs without external pull-ups. Reset input pin. A reset is accomplished by holding the RESET pin high for at least 1ms. even if the oscillator has been stopped. The CPU responds by executing an internal reset. An internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC. This pin does not receive the power down voltage since the function has been transferred to the VCC pin. Address Latch Enable. This output latches for latching the low byte of the address during accesses to external memory. For this purpose, ALE is activated twice every machine cycle or at a constant rate of 1/6th the oscillator frequency, except during an external memory access at which time one ALE pulse is skipped. ALE can drive CMOS inputs without an external pull-up. PSEN Program Store Enable output. This output is the read strobe to external program memory. For this purpose, PSEN is activated twice every machine cycle. (However, when executing out of external program memory, two activations of PSEN are skipped during each access to external data memory.) PSEN is not activated during fetches from internal program memory. It can drive CMOS inputs without an external pull-up. External Access input pin. When EA is held high, the CPU executes out of internal program memory (unless the program counter exceeds 0FFFH). When EA is held low, the CPU executes only out of external program memory. EA must not be floated. XTAL1 XTAL2 Crystal 1 pin. It is an input to the inverting amplifier which forms the internal oscillator. Crystal 2 pin. It is an output of the inverting amplifier that forms the internal oscillator. Description RESET ALE EA 8/38 ¡ Semiconductor MSM80C31F/80C51F DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM 0F0H 0E0H 0D0H 0B8H 0B0H 0A8H 0A0H 99H 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H B ACC PSW IP P3 IE P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0 7F USER RAM 80W ¥ 8 bits 30 2F DATA RAM 20 1F 18 17 10 0F 08 07 00 7F 78 BIT ADDRESSABLE RAM 7 0 R7 BANK 3 R0 R7 BANK 2 R0 R7 BANK 1 R0 R7 BANK 0 R0 SPECIAL FUNCTION REGISTERS BIT ADDRESSING DATA ADDRESSING 9/38 ¡ Semiconductor MSM80C31F/80C51F DETAILED DIAGRAM OF DATA MEMORY (RAM) 7FH 30H 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH Bank 3 18H 17H Bank 2 10H 0FH Bank 1 08H 07H Bank 0 00H 0 8 7 16 15 24 23 REGISTER ADDRESSING 127 USER DATA RAM 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 48 47 46 45 44 43 BIT ADDRESSING INDIRECT ADDRESSING 42 41 40 39 38 37 36 35 34 33 32 31 DATA ADDRESSING 10/38 ¡ Semiconductor MSM80C31F/80C51F DETAILED DIAGRAM OF SPECIAL FUNCITON REGISTERS Special Function Register (LSB) Symbol F2 E2 OV D2 PX1 BA B2 EX1 AA A2 F1 E1 F1 D1 PT0 B9 B1 ET0 A9 A1 F0 E0 P D0 PX0 B8 B0 EX0 A8 A0 B ACC PSW IP P3 IE P2 SBUF TI 99 91 RI 98 90 SCON P1 TH1 TH0 TL1 TL0 TMOD IE0 89 IT0 88 TCON PCON DPH DPL SP 82 81 80 P0 Data Address 0F0H 0E0H 0D0H 0B8H 0B0H 0A8H 0A0H 99H 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H (MSB) F7 E7 CY D7 — B7 EA AF A7 F6 E6 AC D6 — B6 — A6 F5 E5 F0 D5 — B5 — A5 Bit Address F4 E4 RS1 D4 PS BC B4 ES AC A4 F3 E3 RS0 D3 PT1 BB B3 ET1 AB A3 SM0 9F 97 SM1 9E 96 Not Bit Addressable SM2 REN TB8 RB8 9D 9C 9B 9A 95 94 93 92 Not Bit Addressable Not Bit Addressable Not Bit Addressable Not Bit Addressable TF1 8F TR1 8E Not Bit Addressable TF0 TR0 IE1 IT1 8D 8C 8B 8A Not Bit Addressable Not Bit Addressable Not Bit Addressable Not Bit Addressable 87 86 85 84 83 11/38 ¡ Semiconductor MSM80C31F/80C51F INSTRUCTION LIST List of Instruction Symbols : : : : : : : : : : : : : : : : : : : : : : ¨ : Æ : — : < : > : bit address : code address : data : relative offset : direct address : A AB AC B C DPTR PC Rr SP AND OR XOR + – X / (X) ((X)) # @ = Accumulator Register pair Auxiliary carry flag Arithmetic operation register Carry flag Data pointer Program counter Register indicator (r = 0 to 7) Stack pointer Logical product Logical sum Exclusive-OR Addition Subtraction Multiplication Division Denotes the contents of X Denotes the contents of address determined by the contents of X Denotes the immediate data Denotes the indirect address Equality Non-equality Substitution Substitution Negation Smaller than Larger than RAM and the special function register bit specifier address (b0 to b7) Absolute address (A0 to A15) Immediate data (I0 to I7) Relative jump address offset value (R0 to R7) RAM and the special function register byte specifier address (a0 to a7) 12/38 ¡ Semiconductor MSM80C31F/80C51F MSM80C31F/MSM80C51F Instruction Codes L H 0 0000 NOP 1 0001 2 0010 LJMP address 16 LCALL adress 16 RET RETI ORL direct, A ANL direct, A XRL direct, A ORL C, bit ANL C, bit MOV bit, C MOV C, bit CPL bit CLR bit SETB bit MOVX A, @R0 MOVX @R0, A 3 0011 RR A RRC A RL A RLC A ORL direct, #data ANL direct, #data XRL direct, #data JMP @A+DPTR MOVC A, @A+PC MOVC A, @A+DPTR INC DPTR CPL C CLR C SETB C MOVX A, @R1 MOVX @R1, A 4 0100 INC A DEC A ADD A, #data ADDC A, #data ORL A, #data ANL A, #data XRL A, #data MOV A, #data DIV AB SUBB A, #data MUL AB CJNE A, #data rel SWAP A DA A CLR A CPL A 5 0101 INC direct DEC direct ADD A, direct ADDC A, direct ORL A, direct ANL A, direct XRL A, direct MOV direct #data MOV direct1, direct2 SUBB A, direct 6 0110 INC @R0 DEC @R0 ADD A, @R0 ADDC A, @R0 ORL A, @R0 ANL A, @R0 XRL A, @R0 7 0111 INC @R1 DEC @R1 ADD A, @R1 ADDC A, @R1 ORL A, @R1 ANL A, @R1 XRL A, @R1 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 AJMP address 11 (Page 0) ACALL JBC bit, address 11 rel (Page 0) AJMP JB bit, address 11 rel (Page 1) ACALL JNB bit, address 11 rel (Page 1) AJMP JC address 11 rel (Page 2) ACALL JNC rel address 11 (Page 2) AJMP JZ rel address 11 (Page 3) ACALL JNZ rel address 11 (Page 3) AJMP SJMP rel address 11 (Page 4) ACALL MOV DPTR, address 11 #data 16 (Page 4) AJMP ORL C, /bit address 11 (Page 5) ACALL ANL C, /bit address 11 (Page 5) AJMP PUSH address 11 direct (Page 6) ACALL POP address 11 direct (Page 6) AJMP MOVX A, address 11 @DPTR (Page 7) ACALL MOVX address 11 @DPTR, A (Page 7) MOV @R0, MOV @R1, #data #data MOV direct, @R0 SUBB A, @R0 MOV direct, @R1 SUBB A, direct MOV @R0, MOV @R1, direct direct CJNE A, direct, rel XCH A, direct DJNZ direct, rel MOV A, direct MOV direct, A CJNE @R0 CJNE @R1, #data, #data, rel rel XCH A, @R0 XCHD A, @R0 MOV A, @R0 MOV @R0, A XCH A, @R1 XCHD A, @R1 MOV A, @R1 MOV @R1, A 2BYTES MNEMONIC 2CYCLES 3BYTES 4CYCLES 13/38 ¡ Semiconductor MSM80C31F/80C51F MSM80C31F/MSM80C51F Instruction Codes (continued) L H 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 8 1000 INC R0 DEC R0 9 1001 INC R1 DEC R1 A 1010 INC R2 DEC R2 B 1011 INC R3 DEC R3 C 1100 INC R4 DEC R4 D 1101 INC R5 DEC R5 E 1110 INC R6 DEC R6 F 1111 INC R7 DEC R7 ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7 ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7 ANL A, R0 XRL A, R0 MOV R0, #data MOV direct, R0 SUBB A, R0 MOV R0, direct CJNE R0, #data rel XCH A, R0 DJNZ R0, rel ANL A, R1 XRL A, R1 MOV R1, #data MOV direct, R1 SUBB A, R1 MOV R1, direct CJNE R1, #data rel XCH A, R1 DJNZ R1, rel ANL A, R2 XRL A, R2 MOV R2, #data MOV direct, R2 SUBB A, R2 MOV R2, direct CJNE R2, #data rel XCH A, R2 DJNZ R2, rel ANL A, R3 XRL A, R3 MOV R3, #data MOV direct, R3 SUBB A, R3 MOV R3, direct CJNE R3, #data rel XCH A, R3 DJNZ R3, rel ANL A, R4 XRL A, R4 MOV R4, #data MOV direct, R4 SUBB A, R4 MOV R4, direct CJNE R4, #data rel XCH A, R4 DJNZ R4, rel ANL A, R5 XRL A, R5 MOV R5, #data MOV direct, R5 SUBB A, R5 MOV R5, direct CJNE R5, #data rel XCH A, R5 DJNE R5, rel ANL A, R6 XRL A, R6 MOV R6, #data MOV direct, R6 SUBB A, R6 MOV R6, direct CJNE R6, #data rel XCH A, R6 DJNE R6, rel ANL A, R7 XRL A, R7 MOV R7, #data MOV direct, R7 SUBB A, R7 MOV R7, direct CJNE R7, #data rel XCH A, R7 DJNE R7, rel MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A 14/38 ¡ Semiconductor MSM80C31F/80C51F Instruction Set Details Type Mnemonic ADD A, Rr ADD A, direct ADD A, @Rr ADD A, #data ADDC A, Rr ADDC A, direct ADDC A, @Rr Airthmetic operation instructions ADDC A, #data SUBB A, Rr SUBB A, direct SUBB A, @Rr SUBB A, #data MUL AB DIV AB DA A Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 I7 0 0 0 0 I7 1 1 1 1 I7 1 1 1 0 0 0 0 I6 0 0 0 0 I6 0 0 0 0 I6 0 0 1 1 1 1 1 I5 1 1 1 1 I5 0 0 0 0 I5 1 0 0 0 0 0 0 I4 1 1 1 1 I4 1 1 1 1 I4 0 0 1 1 0 0 0 I3 1 0 0 0 I3 1 0 0 0 I3 0 0 0 r2 1 1 1 I2 r2 1 1 1 I2 r2 1 1 1 I2 1 1 1 r1 0 1 0 I1 r1 0 1 0 I1 r1 0 1 0 I1 0 0 0 r0 1 r0 0 I0 r0 1 r0 0 I0 r0 1 r0 0 I0 0 0 0 1 1 1 4 4 1 1 2 1 2 1 1 1 1 (AC), (0V), (C), (A) ¨ (A)–((C))+((Rr)) (AC), (0V), (C), (A) ¨ (A)–((C)+ (direct address)) (AC), (0V), (C), (A) ¨ (A)–((C)+((Rr)) (AC), (0V), (C), (A) ¨ (A)–((C)+ #data) (AB) ¨ (A) x (B) (A)quotient, (B) remainder ¨ (A)/(B) 1 2 1 2 1 1 1 1 (AC), (0V), (C), (A) ¨ (A)+(C)+(Rr) (AC), (0V), (C), (A) ¨ (A)+(C)+ (direct address) (AC), (0V), (C), (A) ¨ (A)+(C)+((Rr)) (AC), (0V), (C), (A) ¨ (A)+(C)+#data Bytes Cycles 1 2 1 2 1 1 1 1 Description (AC), (0V), (C), (A) ¨ (A)+(Rr) (AC), (0V), (C), (A) ¨ (A)+(direct address) (AC), (0V), (C), (A) ¨ (A)+((Rr)) (AC), (0V), (C), (A) ¨ (A)+#data a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 When the contents of accumulator bits 0 thru 3 are greater than 9, or when auxiliary carry (AC) is 1, 6 is added to bits 0 thru 3. Bits 4 thru 7 are then examined, and when bits 4thru 7 follwoing compensation of lower bits 0 thru 3 is greater than 9, or when carry (C) is 1, 6 is added to bits 4 thru 7. As a result, the cary flag can be set, but cannot be cleared. (A) ¨ 0 (A) ¨ (A) C CLR A Accumulation operation instructions CPL A PL A 1 1 0 1 1 0 1 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 Accumulator ¨¨¨¨¨¨¨¨ 7 0 Accumulator ¨¨¨¨¨¨¨¨ 7 0 PL C 0 0 1 1 0 0 1 1 1 1 C 15/38 ¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) Type Mnemonic RR A Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 Bytes Cycles 1 1 C Description Accumulator ÆÆÆÆÆÆÆÆ 7 0 Accumulator ÆÆÆÆÆÆÆÆ 7 0 Accumulation operation instructions RRC A 0 0 0 1 0 0 1 1 1 1 C SWAP A INC A INC Rr INC direct INC @Rr INC DPTR DEC A DEC Rr DEC direct DEC @Rr ANL A, Rr ANL A, direct ANL A, @Rr ANL A, #data 1 0 0 0 0 1 0 0 0 0 0 0 0 0 I7 0 0 I7 1 0 0 0 0 0 0 0 0 0 1 1 1 1 I6 1 1 I6 1 1 1 1 I6 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 I5 0 0 I5 0 0 0 0 I5 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 I4 1 1 I4 0 0 0 0 I4 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 I3 0 0 I3 1 0 0 0 I3 0 1 1 r2 1 1 0 1 r2 1 1 r2 1 1 1 I2 0 0 I2 r2 1 1 1 I2 0 0 0 r1 0 1 1 0 r1 0 1 r1 0 1 0 I1 1 1 I1 r1 0 1 0 I1 1 0 0 r0 1 r0 1 0 r0 1 r0 r0 1 r0 0 I0 0 1 I0 r0 1 r0 0 I0 0 1 1 1 2 1 1 1 1 2 1 1 2 1 2 2 3 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 2 (A4 -7) ´ (A0 -3) (A) ¨ (A)+1 (Rr) ¨ (Rr)+1 (direct address) ¨ (direct address)+1 ((Rr)) ¨ ((Rr))+1 (DPTR) ¨ (DPTR)+1 (A) ¨ (A)–1 (Rr) ¨ (Rr)–1 (direct address) ¨ (direct address)–1 ((Rr)) ¨ ((Rr))–1 (A) ¨ (A) AND (Rr) (A) ¨ (A) AND (direct address) (A) ¨ (A) AND ((Rr)) (A) ¨ (A) AND #data (direct address) ¨ (direct address) AND (A) (direct address) ¨ (direct address) AND #data Increment/decrement a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 Logical operation instructions ANL direct, A ANL direct, #data a7 a6 a5 a4 a7 a6 a5 a4 0 0 0 0 I7 ORL direct, A 0 a3 a2 a1 a0 a3 a2 a1 a0 1 2 1 2 2 1 1 1 1 1 ORL A, Rr ORL A, direct ORL A, @Rr ORL A, #data (A) ¨ (A) OR (Rr) (A) ¨ (A) OR (direct address) (A) ¨ (A) OR ((Rr)) (A) ¨ (A) OR #data (direct address) ¨ (direct address) OR (A) a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 16/38 ¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) Type Mnemonic ORL direct, #data Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 I7 1 I6 1 1 1 1 I6 1 1 I6 1 I6 1 I6 1 I6 1 I6 0 I6 1 1 0 0 0 1 0 0 I5 1 1 1 1 I5 1 1 I5 1 I5 1 I5 1 I5 1 I5 0 I5 0 0 1 0 1 1 1 0 I4 0 0 0 0 I4 0 0 I4 1 I4 1 I4 1 I4 1 I4 1 I4 0 1 1 0 1 1 0 0 I3 1 0 0 0 I3 0 0 I3 0 I3 1 I3 0 I3 0 I3 0 I3 0 0 0 0 0 0 0 0 I2 r2 1 1 1 I2 0 0 I2 1 I2 r2 I2 1 I2 1 I2 0 I2 0 0 0 0 0 0 0 1 I1 r1 0 1 0 I1 1 1 I1 0 I1 r1 I1 0 I1 1 I1 0 I1 1 1 1 1 0 1 0 1 I0 r0 1 r0 0 I0 0 1 I0 0 I0 r0 I0 1 I0 r0 I0 0 I8 I0 1 1 1 0 0 0 0 1 1 1 2 2 2 2 1 1 1 2 2 2 2 (C) ¨ 0 (C) ¨ 1 (C) ¨ (C) (C) ¨ (C) AND (bit address) (C) ¨ (C) AND (bit address) (C) ¨ (C) OR (bit address) (C) ¨ (C) OR (bit address) 3 2 (DPTR) ¨ #data 16 2 1 (Rr)) ¨ #data 3 2 (direct address) ¨ #data 2 1 (Rr) ¨ #data 2 1 (A) ¨ #data 2 3 1 2 (direct address) ¨ (direct address) XOR (A) (direct address) ¨ (direct address) XOR #data 1 2 1 2 1 1 1 1 (A) ¨ (A) XOR (Rr) (A) ¨ (A) XOR (direct address) (A) ¨ (A) XOR ((Rr)) (A) ¨ (A) XOR #data a7 a6 a5 a4 0 0 0 0 I7 XRL direct, A XRL direct, #data 0 0 I7 MOV A, #data 0 I7 MOV Rr, #data MOV direct, #data 0 I7 0 I7 MOV @Rr, #data MOV DPTR, #data 16 0 I7 1 I7 CLR C 1 1 1 1 1 0 1 a3 a2 a1 a0 Bytes Cycles 3 2 Description (direct address) ¨ (direct address) OR #data Logical operation instructions XRL A, Rr XRL A, direct XRL A, @Rr XRL A, #data a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a7 a6 a5 a4 a3 a2 a1 a0 a3 a2 a1 a0 Immediate data setting instructions a7 a6 a5 a4 a3 a2 a1 a0 I15 I14 I13 I12 I11 I10 I9 Carry flag operation instructions SETB C CPL C ANL C, bit ANL C,/bit ORL C, bit ORL C,/bit b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 17/38 ¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) Type Mnemonic MOV C, bit MOV bit, C SETB bit Instruction code D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 a7 1 a7 Bytes Cycles 2 2 2 2 2 1 2 1 1 2 2 2 3 1 2 1 1 1 1 1 1 1 2 1 2 2 Description (C) ¨ (bit address) (bit address) ¨ (C) (bit address) ¨ 1 (bit address) ¨ 0 (bit address) ¨ (bit address) (A) ¨ (Rr) (A) ¨ (direct address) (A) ¨ ((Rr)) (Rr) ¨ (A) (Rr) ¨ (direct address) (direct address) ¨ (A) (direct address) ¨ (Rr) (direct address 1) ¨ (direct address 2) Carry flag operation instructions 0 0 1 1 0 1 1 1 1 0 1 0 0 2 a6 1 a6 1 0 0 0 1 1 1 1 1 1 1 0 0 2 a5 1 a5 0 1 1 0 1 0 0 0 1 0 1 0 0 2 a4 1 a4 0 0 0 0 0 1 0 0 1 1 0 1 0 2 a3 1 a3 0 0 0 0 0 r2 1 1 r2 r2 1 r2 1 2 a2 1 a2 1 1 1 1 1 r1 0 1 r1 r1 0 r1 1 2 a1 1 a1 0 0 0 0 0 r0 1 r0 r0 r0 1 r0 r0 2 a0 1 a0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 CLR bit CPL bit MOV A, Rr MOV A, direct MOV A, @Rr MOV Rr, A b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Bit operation instructions a7 a6 a5 a4 a3 a2 a1 a0 Data transfer instructions MOV Rr, direct MOV direct, A MOV direct, Rr MOV direct 1, direct 2 a7 a6 a5 a4 a7 a6 a5 a4 a7 a6 a5 a4 a3 a2 a1 a0 a3 a2 a1 a0 a3 a2 a1 a0 MOV @Rr, A MOV @Rr, direct 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 r2 1 1 1 1 1 1 1 r1 0 1 1 r0 r0 1 1 r0 1 r0 r0 1 2 1 1 1 2 1 1 1 2 2 2 1 2 1 1 ((Rr)) ¨ (A) ((Rr)) ¨ (direct address) (A) ¨ ((A)+(DPTR)) (PC) ¨ (PC+1) (A) ¨ ((A)+(PC)) (A) ´ (Rr) (A) ´ (direct address) (A) ´ ((Rr)) (A0 - 3) ´ ((Rr0 - 3)) a7 a6 a5 a4 a3 a2 a1 a0 Constant code instructions Data exchange instructions MOVC A, @A+DPTR MOVC A, @A+PC XCH A, Rr XCH A, direct XCH A, @Rr XCHD A, @Rr a7 a6 a5 a4 a3 a2 a1 a0 18/38 ¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) Type Mnemonic PUSH direct POP direct ACALL addr 11 Instruction code D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 a7 a6 a5 a4 a7 a6 a5 a4 A10 A9 A8 a3 a2 a1 a0 2 2 2 2 a3 a2 a1 a0 Bytes Cycles 2 2 Description (SP) ¨ (SP)+1 ((SP)) ¨ (direct address) (direct address) ¨ ((SP)) (SP) ¨ (SP)–1 (PC) ¨ (PC)+2 (SP) ¨ (SP)+1 ((SP)) ¨ (PC0 - 7) (SP) ¨ (SP)+1 ((SP)) ¨ (PC8 - 15) (PC0 - 10) ¨ A0 - 10 (PC) ¨ (PC)+3 (SP) ¨ (SP)+1 ((SP)) ¨ (PC0 - 7) (SP) ¨ (SP)+1 ((SP)) ¨ (PC8 - 15) (PC0 - 10) ¨ A0 - 10 (PC8 - 15) ¨ ((SP)) (SP) ¨ (SP)–1 (PC0 - 7) ¨ ((SP)) (SP) ¨ (SP)–1 (PC8 - 15) ¨ ((SP)) (SP) ¨ (SP)–1 (PC0 - 7) ¨ ((SP)) (SP) ¨ (SP)–1 (PC) ¨ (PC)+2 (PC0 - 10) ¨ A0 - 10 (PC0 - 15) ¨ A0 - 15 A7 A6 A5 A4 A3 A2 A1 A0 Subroutine instructions LCALL addr 16 0 0 0 1 0 0 1 0 3 2 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RET 0 0 1 0 0 0 1 0 1 2 RETI 0 0 1 1 0 0 1 0 1 2 AJMP addr 11 A10 A9 A8 0 0 0 0 0 0 0 0 0 0 1 1 0 2 3 2 2 Jump instructions A7 A6 A5 A4 A3 A2 A1 A0 LJMP addr 16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SJMP rel JMP @A+ DPTR 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 2 1 2 2 R7 R6 R5 R4 R3 R2 R1 R0 (PC) ¨ (PC)+3 (SP) ¨ (SP)+1 (PC) ¨ (A)+(DPTR) 19/38 ¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) Type Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 a3 a2 a1 a0 Bytes Cycles 3 2 Description (PC) ¨ (PC)+3 IF (A)π(direct address) THEN (PC) ¨ (PC)+relative offset IF (A)