MSM9210

E2C0038-39-95 ¡ Semiconductor ¡ Semiconductor MSM9210 GENERAL DESCRIPTION This version: Sep. 1999 MSM9210 Previous version: Aug. 1999 32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming The MSM9210 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 32-segment driver multiplexed to drive up to 96 segments, and 10-bit digital dimming circuit. MSM9210 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. MSM9210 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS. FEATURES • Logic supply voltage (VDD) : 4.5 to 5.5V : 8 to 18V • Driver supply voltage (VDISP) • Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI=1/2 duty selectable at "H" level DUP/TRI=1/3 duty selectable at "L" level • Number of display segments Max. 64-segment display (during 1/2 duty mode) Max. 96-segment display (during 1/3 duty mode) • Master/Slave selectable M/S=Master mode selectable at "H" level M/S=Slave mode selectable at "L" level • Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN • 32-segment driver outputs : IOH=–5mA at VOH=VDISP–0.8V (SEG1 to 22) (can be directly connected to VFD tube : IOH=–10mA at VOH=VDISP–0.8V (SEG23 to 32) and require no external resisters) : IOL=500mA at VOL=2V (SEG1 to 32) • 3-grid pre-driver outputs : IOH=–5.0mA at VOH=VDISP–0.8V (require external drivers) IOL=10mA at VOL=2V • Logic outputs : IOH=–200mA at VOH=VDD–0.8V IOL=200mA at VOL=0.8V • Built-in digital dimming circuit (10-bit resolution) • Built-in oscillation circuit (external R and C) • Built-in Power-On-Reset circuit • Package options: 56-pin plastic QFP (QFP56-P-910-0.65-2K) Product name: MSM9210GS-2K 64-pin plastic QFP (QFP64-P-1414-0.80-BK) Product name: MSM9210GS-BK 1/19 ¡ Semiconductor MSM9210 BLOCK DIAGRAM GRID1 GRID2 GRID3 SEG1 SEG32 VDISP D-GND VDD L-GND 0H 32 Segment Driver 3 Grid pre Driver Power On Reset 4H POR Out1-32 96 to 32 Segment Control in1-32 in1-32 in1-32 1H Mode Select POR 0H POR in1-3 Out1-32 Segment Latch 1 in1-32 2H 0H POR Out1-32 Segment Latch 2 in1-32 3H 0H POR Out1-32 Segment Latch 3 in1-32 CS CLOCK DATA IN Control Out1-3 3bit Shift Register POR Out1-32 32bit Shift Register 4H POR in1-10 Dimming Latch Out1-10 POR OSC0 OSC1 DIM IN SYNC IN1 SYNC IN2 M/S DUP/TRI OSC POR 10bit Digital Dimming DIM OUT SYNC OUT1 Timing Generator SYNC OUT2 2/19 ¡ Semiconductor MSM9210 INPUT AND OUTPUT CONFIGURATION Schematic Diagram of Driver Output Circuit VDISP VDISP OUTPUT D-GND D-GND 3/19 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 GRID1 GRID2 10 GRID3 11 D-GND 12 NC 13 VDD 14    49 D-GND 55 SEG24 54 SEG23 53 SEG22 52 SEG21 51 SEG20 50 SEG19 48 SEG18 47 SEG17 46 SEG16 56 VDISP 1 2 3 4 5 6 7 8 9 MSM9210 45 SEG15 44 SEG14 43 VDISP 42 SEG13 41 SEG12 40 SEG11 39 SEG10 38 SEG9 37 SEG8 36 SEG7 35 SEG6 34 SEG5 33 SEG4 32 SEG3 31 SEG2 30 SEG1 29 NC DIM IN 15 SYNC IN 1 16 SYNC IN 2 17 CS 18 CLOCK 19 DATA IN 20 L-GND 21 OSC1 22 OSC0 23 DUP/TRI 24 M/S 25 SYNC OUT 2 26 SYNC OUT 1 27 NC: No connection 56-pin Plastic QFP DIM OUT 28 4/19 ¡ Semiconductor MSM9210 56 D-GND 55 SEG18 62 SEG24 61 SEG23 60 SEG22 59 SEG21 58 SEG20 57 SEG19 54 SEG17 53 SEG16 52 SEG15 51 SEG14 64 VDISP 63 NC NC SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 50 NC 49 VDISP 48 NC 47 NC 46 SEG13 45 SEG12 44 SEG11 43 SEG10 42 SEG9 41 SEG8 40 SEG7 39 SEG6 38 SEG5 37 SEG4 36 SEG3 35 SEG2 34 SEG1 33 NC 1 2 3 4 5 6 7 8 9 GRID1 10 GRID2 11 GRID3 12 D-GND 13 NC 14 VDD 15 NC 16 NC 17 DIM IN 18 SYNC IN1 19 SYNC IN2 20 CS 21 CLOCK 22 DATA IN 23 L-GND 24 OSC1 25 OSC0 26 DUP/TRI 27 M/S 28 SYNC OUT2 29 SYNC OUT1 30 NC: No connection 64-pin Plastic QFP DIM OUT 31 NC 32 5/19 ¡ Semiconductor MSM9210 PIN DESCRIPTIONS Pin QFP56 43,56 14 12, 49 21 30 to 42, SEG1 to 22 44 to 48, 50 to 53 QFP64 49,64 15 13, 56 24 34 to 46, 51 to 55, 57 to 60 O Symbol VDISP VDD D-GND L-GND Type — — — — Description Power supply pins for VFD driver circuit. 43 pin and 56 pin should be connected externally. Power supply pin for logic drive. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. 12pin, 21pin and 49pin should be connected externally. Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH£–5 mA Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH£–10 mA Inverted Grid signal output pins. SEG23 to 32 1 to 8, 54, 55 2 to 9, 61, 62 O GRID1 to 3 9, 10, 11 10, 11, 12 O For pre-driver, the external circuit is required. IOL£10 mA Chip select input pin. Data is not transferred when CS is set to a Low level. Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to L-GND. Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. Dimming pulse input. When the slave mode is selected, the pulse width of the all segment output are controlled by a input pulse width of DIM IN. Connect this pin to the master side DIM OUT pin at the slave mode. When the master mode is selected, the input level of this pin is ignored and the pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. Connect this pin to VDD or L-GND at the master mode. CS CLOCK DATA IN 18 19 20 21 22 23 I I I DUP/TRI 24 27 I M/S 25 28 I DIM IN 15 18 I 6/19 ¡ Semiconductor MSM9210 Symbol Pin QFP56 QFP64 Type Description Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYNC OUT 1, and 2 pins. When the master mode is selected, the input level of these pins are ignored. Connect these pins to VDD or L-GND at the master mode. Dimming pulse output. Connect this pin to the slave side DIM IN pin. Synchronous signal output. Connect these pins to the slave side SYNC IN 1, and 2 pins. RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details, refer to ELECTRICAL CHARACTERISTICS. OSC0 R OSC1 C SYNC IN 1, 2 16, 17 19, 20 I DIM OUT SYNC OUT 1, 2 OSC0 28 26, 27 23 31 29, 30 26 O O I OSC1 22 25 O ABSOLUTE MAXIMUM RATING Parameter Driver Supply Voltage Logic Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP VDD VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Condition — — — Ta≥25°C — SEG1 to 22 SEG23 to 32 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Ratings –0.3 to +20 –0.3 to +6.5 –0.3 to VDD+0.3 360 –55 to +150 –10.0 to +2.0 –20.0 to +2.0 –10.0 to +20.0 –2.0 to +2.0 Unit V V V mW °C mA mA mA mA RECOMMENDED OPERATING CONDITIONS Parameter Driver Supply Voltage Logic Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Operating Temperature Symbol VDISP VDD VIH VIL fC TOP Condition — — All inputs except OSC0 All inputs except OSC0 — — Min. 8.0 4.5 0.8VDD — — –40 Typ. 13.0 5.0 — — — — Max. 18.0 5.5 — 0.2VDD 1.0 +85 Unit V V V V MHz °C 7/19 ¡ Semiconductor When a 1/2 duty VFD tube is used Parameter Oscillation Frequency Frame Frequency Symbol fOSC fFR Condition R=8.2KW±5%, C=22pF±5% R=8.2KW±5%, C=22pF±5% Min. 1.0 122 Typ. 1.5 183 MSM9210 Max. 2.0 244 Unit MHz Hz When a 1/3 duty VFD tube is used Parameter Oscillation Frequency Frame Frequency Symbol fOSC fFR Condition R=6.2KW±5%, C=22pF±5% R=6.2KW±5%, C=22pF±5% Min. 1.5 122 Typ. 2.25 183 Max. 3.0 244 Unit MHz Hz 8/19 ¡ Semiconductor MSM9210 ELECTRICAL CHARACTERISTICS DC Characteristics Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol Applied pin VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 Supply Current IDISP IDD *1) *1) *1) *1) SEG1-22 SEG23-32 GRID1-3 *2) SEG1-22 SEG23-32 GRID1-3 *2) VDISP VDD VDD=4.5V VDD=4.5V Condition — — VIH=VDD VIL=GND IOH1=–5mA VDISP=9.5V IOH2=–10mA IOH3=–5mA IOH4=–200mA IOL1=500mA VDISP=9.5V IOL2=500mA IOL3=10mA IOL4=200mA fOSC=3.0MHz, no load fOSC=3.0MHz, no load Min. 0.8VDD — –1.0 –1.0 VDISP–0.8 VDISP–0.8 VDISP–0.8 VDD–0.8 — — — — — — Max. — 0.2VDD +1.0 +1.0 — — — — 2.0 2.0 2.0 0.8 100 5.0 Unit V V mA mA V V V V V V V V mA mA *1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT 1, SYNC OUT 2 9/19 ¡ Semiconductor AC Characteristics MSM9210 Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) CS Wait Time Output Slew Rate Time VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tRSOFF tR tF tPRZ tPOF CL=100pF Condition — — — — — — — — tR=20% to 80% tF=80% to 20% Min. — 400 400 400 20 400 400 400 — — — 5.0 Max. 1.0 — — — — — — — 2.0 2.0 100 — Unit MHz ns ns ns ms ns ns ms ms ms ms ms Mounted in a unit Mounted in a unit, VDD=0.0V TIMING DIAGRAM l Data Input Timing tCSS 1/fC CLOCK tDS DATA IN VALID VALID tDH VALID VALID tCW tCW tCSH tCSL –0.8VDD –0.2VDD –0.8VDD –0.2VDD –0.8VDD –0.2VDD CS l Reset Timing tPRZ tRSOFF CS tPOF –0.8VDD –0.0V –0.8VDD –0.0V VDD l Driver Output Timing tR tF tR –0.8VDISP –0.2VDISP SEG1-32, GRID1-3 10/19 ¡ Semiconductor l Output Timing (Duplex Operation) *1bit time=4/fOSC (The dimming data is 1016/1024 at the master mode) 2048bit times (1 display cycle) GRID1 1016bit times 8bit times GRID2 1016bit times 1016bit times 8bit times MSM9210 VDISP 8bit times D-GND VDISP D-GND VDISP GRID3 3bit times SEG1-32 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1029bit times 5bit times 5bit times 5bit times 5bit times D-GND VDISP D-GND VDD L-GND VDD L-GND VDD L-GND l Output Timing (Triplex Operation) *1bit time=4/fOSC (The dimming data is 1016/1024 at the master mode) 3072bit times (1 display cycle) GRID1 1016bit times 8bit times GRID2 1016bit times 8bit times GRID3 3bit times SEG1-32 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 1016bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 5bit times 5bit times 5bit times D-GND VDISP D-GND VDISP D-GND VDD L-GND VDD L-GND VDD L-GND 8bit times VDISP D-GND VDISP 11/19 ¡ Semiconductor MSM9210 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, MSM9210 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: • The contents of the shift registers and latches are set to "0". • The digital dimming duty cycle is set to "0". • All segment outputs are set to Low level. • All grid outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows: FUNCTION MODE 0 1 2 3 4 OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input FUNCTION DATA M0 0 1 0 1 0 M1 0 0 1 1 0 M2 0 0 0 0 1 Segment Data Input [Function Mode: 0 to 3] • MSM9210 receives the segment data when function mode 0 to 3 are selected. • The same segment data is transferred to the 3 segment data latches corresponding to GRID 1 to 3 at the same time when the function mode 0 is selected. • The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. • Segment output (SEG1 to 32) becomes High level (lightning) when the segment data (S1 to S32) is set to "1". [Data Format] Input Data : 35 bits Segment Data : 32 bits Mode Data : 3 bits Bit Input Data 1 S1 2 S2 3 S3 4 S4 29 30 31 32 33 M0 34 M1 35 M2 S29 S30 S31 S32 Segment Data (32bits) Mode Data (3bits) 12/19 ¡ Semiconductor [Bit correspondence between segment output and segment data] SEG n SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSM9210 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 Digital Dimming Data Input [Function Mode: 4] • MSM9210 receives the digital dimming data when function mode 4 is selected. • The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. • The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data: 10 bits Mode Data : 3 bits Bit Input Data 1 D1 LSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 11 12 13 Digital Dimming Data (10bits) D10 M0 M1 M2 MSB Mode Data (3bits) (MSB) (LSB) D1 0 1 1 0 1 1 D2 0 0 1 0 0 1 D3 0 0 1 0 0 1 D4 0 0 0 1 1 1 Dimming Data D5 0 0 1 1 1 1 D6 0 0 1 1 1 1 D7 0 0 1 1 1 1 D8 0 0 1 1 1 1 D9 0 0 1 1 1 1 D10 0 0 1 1 1 1 Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024 Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: • The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be connected to L-GND or VDD. • The pulse width of GRID1 to 3 and SEG1 to 32 are controlled by the internal digital dimming circuit. • The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing generator. 13/19 ¡ Semiconductor MSM9210 Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: • The internal dimming circuit is ignored. • The pulse width of SEG1 to 32 are controlled by the pulse width of DIM IN signal. • The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2 signals. • The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level. [Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 32] SYNC IN 1 0 1 0 1 SYNC IN 2 0 0 1 1 Segment Latch No Latch1 Latch2 Latch3 GRID No GRID1 GRID2 GRID3 DIM IN 0 1 Note: Low: Lights OFF High: Lights ON SEG1 to 32 Low High 14/19 ¡ Semiconductor 1. Circuit for the duplex VFD tube with 128 segments (2 Grid ¥ 64 Anode) APPLICATION CIRCUITS VDD VDD VDISP VDD VDISP SEG1 SEG32 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT GND VDD VDD VDISP SEG1 SEG32 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT S1 S2 S3 G1 G2 S62 S63 S64 MSM9210 (MASTER) DUP/TRI M/S SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND MSM9210 (SLAVE) DUP/TRI M/S SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND Microcontroller GND Duplex VF Tube Ef R C GND R D-GND C GND D-GND MSM9210 GND 15/19 ¡ Semiconductor 2. Circuit for the triplex VFD tube with 192 segments (3 Grid ¥ 64 Anode) VDD VDD VDISP VDD M/S DUP/TRI SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND VDISP SEG1 SEG32 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT GND M/S VDD VDISP SEG1 SEG32 GRID1 GRID2 GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT S1 S2 S3 G1 G2 G3 S62 S63 S64 MSM9210 (MASTER) MSM9210 (SLAVE) DUP/TRI SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND Microcontroller GND Triplex VF Tube Ef R C GND R D-GND C GND D-GND MSM9210 GND 16/19 ¡ Semiconductor MSM9210 NOTES ON TURNING POWER ON/OFF • Connect L-GND and D-GND externally to be an equal potential voltage. • To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after tuning off the driver power supply. [Voltage] VDISP VDD [Time] 17/19 ¡ Semiconductor MSM9210 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor MSM9210 (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation. 2. 3. 4. 5. 6. 7. 8. 9. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan