Revised August 2000
100331
Low Power Triple D-Type Flip-Flop
General Description
Features
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CPn),
Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters
a master when both CPn and CPC are LOW and transfers
to a slave when CPn or CPC (or both) go HIGH. The Master
Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kΩ pull-down
resistors.
■ 35% power reduction of the 100131
■ 2000V ESD protection
■ Pin/function compatible with 100131
■ Voltage compensated operating range = −4.2V to −5.7V
■ Available to industrial grade temperature range
Ordering Code:
Order Number
Package Number
Package Description
100331SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
Description
28-Pin PLCC
CP0–CP2
Individual Clock Inputs
CPC
Common Clock Input
D0–D2
Data Inputs
CD0–CD2
Individual Direct Clear Inputs
SDn
Individual Direct Set Inputs
MR
Master Reset Input
MS
Master Set Input
Q0-Q2
Data Outputs
Q0–Q2
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation
DS010262
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100331 Low Power Triple D-Type Flip-Flop
February 1990
100331
Truth Tables
Synchronous Operation (Each Flip-Flop)
Inputs
Dn
L
H
L
CPn
L
H
L
X
L
X
X
MS
MR
SDn
CDn
L
L
L
L
CPC
L
Asynchronous Operation (Each Flip-Flop)
Outputs
Inputs
MR
SDn
CDn
Qn(t + 1)
Dn
CPn
CPC
L
L
X
X
X
H
L
L
H
X
X
X
L
H
L
L
L
X
X
X
H
H
U
L
L
H
L
L
L
Qn(t)
H
X
L
L
Qn(t)
X
H
L
L
Qn(t)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
U = Undefined
t = Time before CP Positive Transition
t + 1 = Time after CP Positive Transition
= LOW-to-HIGH Transition
Logic Diagram
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Outputs
MS
2
Qn(t + 1)
H
Storage Temperature (TSTG)
Pin Potential to Ground Pin (VEE)
Recommended Operating
Conditions
−65°C to +150°C
+150°C
Maximum Junction Temperature (TJ)
Case Temperature (TC)
−7.0V to +0.5V
−5.7V to −4.2V
Supply Voltage (VEE)
−50 mA
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
≤ 2000V
ESD (Note 2)
−40°C to +85°C
Industrial
Output Current
(DC Output HIGH)
0°C to +85°C
Commercial
VEE to +0.5V
Input Voltage (DC)
100331
Absolute Maximum Ratings(Note 1)
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 3)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C
Min
Typ
Max
Units
VOH
Symbol
Output HIGH Voltage
Parameter
−1025
−955
−870
mV
VIN = VIH (Max)
Conditions
Loading with
VOL
Output LOW Voltage
−1830
−1705
−1620
mV
or VIL (Min)
50Ω to −2.0V
−1035
mV
VIN = VIH (Min)
Loading with
−1610
mV
or VIL (Max)
50Ω to −2.0V
VOHC
Output HIGH Voltage
VOLC
Output LOW Voltage
VIH
Input HIGH Voltage
−1165
−870
mV
Guaranteed HIGH Signal
VIL
Input LOW Voltage
−1830
−1475
mV
Guaranteed LOW Signal
IIL
Input LOW Current
0.5
µA
VIN = VIL (Min)
IIH
Input HIGH Current
IEE
Power Supply Current
for All Inputs
for All Inputs
−122
240
µA
VIN = VIH (Max)
−65
mA
Inputs OPEN
Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
3
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100331
Commercial Version (Continued)
DIP AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
TC = 0°C
Parameter
Min
fMAX
Toggle Frequency
tPLH
Propagation Delay
tPHL
CPC to Output
tPLH
Propagation Delay
tPHL
CPn to Output
tPLH
Propagation Delay
tPHL
CDn, SDn to Output
tPLH
tPHL
tPLH
Propagation Delay
tPHL
MS, MR to Output
tPLH
tPHL
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
TC = +25°C
Max
375
Min
Max
375
TC = +85°C
Min
Units
Conditions
Max
375
MHz
0.75
2.00
0.75
2.00
0.75
2.00
ns
0.75
2.00
0.75
2.00
0.75
2.00
ns
0.70
1.70
0.70
1.70
0.70
1.80
Figures 2, 3
Figures 1, 3
CPn, CPC = L
ns
0.70
2.00
0.70
2.00
0.70
2.00
CPn, CPC = H
1.10
2.60
1.10
2.60
1.10
2.60
CPn, CPC = L
1.10
2.80
1.10
2.80
1.10
2.80
0.35
1.30
0.35
1.30
0.35
1.30
Figures 1, 4
ns
CPn, CPC = H
ns
Figures 1, 3, 4
Figure 5
Dn
0.40
0.40
0.40
CDn, SDn (Release Time)
1.30
1.30
1.30
MS, MR (Release Time)
2.30
2.30
2.30
0.5
0.5
0.7
ns
Figure 5
2.00
2.00
2.00
ns
Figures 3, 4
tH
Hold Time Dn
tPW(H)
Pulse Width HIGH
CPn, CPC, CDn,
ns
Figure 4
SDn, MR, MS
SOIC and PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = 0°C
Min
fMAX
Toggle Frequency
tPLH
Propagation Delay
tPHL
CPC to Output
tPLH
Propagation Delay
tPHL
CPn to Output
tPLH
Propagation Delay
tPHL
CDn, SDn to Output
tPLH
tPHL
tPLH
Propagation Delay
tPHL
MS, MR to Output
tPLH
tPHL
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
Dn
Max
400
TC = +25°C
Min
Max
400
TC = +85°C
Min
Units
Conditions
Max
400
MHz
0.75
1.80
0.75
1.80
0.75
1.80
ns
0.75
1.80
0.75
1.80
0.75
1.80
ns
0.70
1.50
0.70
1.50
0.70
1.60
Figures 2, 3
Figures 1, 3
CPn, CPC =L
ns
0.80
1.80
0.70
1.80
0.70
1.80
1.10
2.40
1.10
2.40
1.10
2.40
1.10
2.60
1.10
2.60
1.10
2.60
0.35
1.10
0.35
1.10
0.35
1.10
CPn, CPC = H
Figures 1, 4
ns
CPn, CPC = L
CPn, CPC = H
ns
Figures 1, 3, 4
Figure 5
0.30
0.30
0.30
CDn, SDn (Release Time)
1.20
1.20
1.20
MS, MR (Release Time)
2.20
2.20
2.20
0.5
0.5
0.7
ns
Figure 5
2.00
2.00
2.00
ns
Figures 3, 4
tH
Hold Time Dn
tPW(H)
Pulse Width HIGH
CPn, CPC, CDn,
SDn, MR, MS
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4
ns
Figure 4
Symbol
(Continued)
Parameter
tPLH
Propagation Delay
tPHL
CPC to Output
tPLH
Propagation Delay
tPHL
CPn to Output
tPLH
Propagation Delay
tPHL
CDn, SDn to Output
tPLH
tPHL
tPLH
Propagation Delay
tPHL
MS, MR to Output
tPLH
TC = 0°C
TC = +25°C
TC = +85°C
Units
Min
Max
Min
Max
Min
Max
0.75
1.40
0.75
1.40
0.80
1.50
ns
0.70
1.40
0.75
1.40
0.80
1.50
ns
0.70
1.50
0.70
1.50
0.80
1.60
CPn, CPC =L
ns
0.80
1.70
0.80
1.70
0.80
1.80
1.10
2.00
1.10
2.00
1.20
2.10
1.20
2.10
1.30
CPn, CPC = H
CPn, CPC = L
ns
2.10
PLCC Only
PLCC Only
2.20
Figures 1, 4
PLCC Only
CPn, CPC = H
PLCC Only
Maximum Skew Common Edge
Output-to-Output Variation
Conditions
Figures 1, 3 PLCC Only
1.20
tPHL
tOSHL
100331
Commercial Version
PLCC Only
100
100
100
ps
(Note 4)
235
235
235
ps
(Note 4)
120
120
120
ps
(Note 4)
275
275
275
ps
(Note 4)
ps
PLCC Only
125
125
125
265
265
265
90
90
90
ps
(Note 4)
90
90
90
ps
(Note 4)
Common Clock to Output Path
tOSHL
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
CPn to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
Common Clock to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
CPn to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
(Note 4)
Common Clock to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
ps
PLCC Only
(Note 4)
CPn to Output Path
tPS
Maximum Skew
Pin (Signal) Transition Variation
PLCC Only
Common Clock to Output Path
tPS
Maximum Skew
Pin (Signal) Transition Variation
PLCC Only
CPn to Output Path
Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design.
5
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100331
Industrial Version
PLCC DC Electrical Characteristics (Note 5)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C
TC = −40°C
TC = 0°C to +85°C
Symbol
Parameter
Min
Max
Min
Max
Units
Conditions
VOH
Output HIGH Voltage
−1085
−870
−1025
−870
mV
VIN = VIH (Max)
VOL
Output LOW Voltage
−1830
−1575
−1830
−1620
mV
or VIL (Min)
50Ω to −2.0V
VOHC
Output HIGH Voltage
−1095
mV
VIN = VIH (Min)
Loading with
VOLC
Output LOW Voltage
−1610
mV
or VIL (Max)
50Ω to −2.0V
VIH
Input HIGH Voltage
−1170
−870
−1165
−870
mV
Guaranteed HIGH Signal
VIL
Input LOW Voltage
−1830
−1480
−1830
1475
mV
Guaranteed LOW Signal
IIL
Input LOW Current
0.5
IIH
Input HIGH Current
IEE
Power Supply Current
−1035
−1565
Loading with
for All Inputs
for All Inputs
µA
0.5
300
−122
−60
−122
VIN = VIL (Min)
240
µA
VIN = VIH (Max)
−65
mA
Inputs Open
Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
TC = −40°C
Symbol
Parameter
Min
Max
fMAX
Toggle Frequency
tPLH
Propagation Delay
tPHL
CPC to Output
tPLH
Propagation Delay
tPHL
CPn to Output
tPLH
Propagation Delay
tPHL
CDn, SDn to Output
tPLH
tPHL
tPLH
Propagation Delay
tPHL
MS, MR to Output
tPLH
tPHL
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
Dn
375
TC = +25°C
Min
Max
400
TC = +85°C
Min
Max
400
Units
MHz
0.75
1.80
0.75
1.80
0.75
1.80
ns
0.70
1.80
0.75
1.80
0.75
1.80
ns
0.60
1.50
0.70
1.50
0.70
1.60
Conditions
Figures 2, 3
Figures 1, 3
CPn, CPC = L
ns
0.70
1.80
0.70
1.80
0.70
1.80
CPn, CPC = H
1.10
2.40
1.10
2.40
1.10
2.40
CPn, CPC = L
1.10
2.60
1.10
2.60
1.10
2.60
0.20
1.40
0.35
1.10
0.35
Figures 1, 4
ns
1.00
0.30
0.30
1.10
CPn, CPC = H
ns
Figures 1, 3, 4
Figure 5
CDn, SDn (Release Time)
1.50
1.20
1.20
MS, MR (Release Time)
2.50
2.20
2.20
0.7
0.5
0.7
ns
Figure 5
2.00
2.00
2.00
ns
Figures 3, 4
tH
Hold Time Dn
tPW(H)
Pulse Width HIGH
CPn, CPC, CDn,
SDn, MR, MS
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6
ns
Figure 4
100331
Test Circuits
FIGURE 1. AC Test Circuit
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = Equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
FIGURE 2. Toggle Frequency Test Circuit
7
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100331
Switching Waveforms
FIGURE 3. Propagation Delay (Clock) and Transition Times
FIGURE 4. Propagation Delay (Resets)
FIGURE 5. Data Setup and Hold Time
Note:
tS is the minimum time before the transition of the clock that information must be present at the data input.
tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.
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8
100331
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
9
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100331 Low Power Triple D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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