1SMB15CAT3

1SMB10CAT3 Series Watt Peak Power Zener Transient Voltage Suppressors Bidirectional* http://onsemi.com The SMB series is designed to protect voltage sensitive components from high voltage, high energy transients. They have excellent clamping capability, high surge capability, low zener impedance and fast response time. The SMB series is supplied in ON Semiconductor’s exclusive, cost-effective, highly reliable Surmetict package and is ideally suited for use in communication systems, automotive, numerical controls, process controls, medical equipment, business machines, power supplies and many other industrial/consumer applications. Features PLASTIC SURFACE MOUNT ZENER OVERVOLTAGE TRANSIENT SUPPRESSORS 10−78 V, 600 W PEAK POWER • • • • • • • • • Working Peak Reverse Voltage Range − 10 V to 75 V Standard Zener Breakdown Voltage Range − 11.7 V to 91.7 V Peak Power − 600 Watts @ 1 ms ESD Rating of Class 3 (> 16 KV) per Human Body Model Maximum Clamp Voltage @ Peak Pulse Current Low Leakage < 5 mA Above 10 V UL 497B for Isolated Loop Circuit Protection Response Time is Typically < 1 ns Pb−Free Packages are Available SMB CASE 403C PLASTIC MARKING DIAGRAM Mechanical Characteristics CASE: Void-free, transfer-molded, thermosetting plastic FINISH: All external surfaces are corrosion resistant and leads are ALYW xxCG G A Y WW xxC = Assembly Location = Year = Work Week = Specific Device Code = (See Table on Page 3) G = Pb−Free Package (Note: Microdot may be in either location) readily solderable MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 Seconds LEADS: Modified L−Bend providing more contact area to bond pads POLARITY: Polarity band will not be indicated MOUNTING POSITION: Any ORDERING INFORMATION Device* 1SMBxxCAT3 1SMBxxCAT3G Package SMB SMB (Pb−Free) Shipping † 2500/Tape & Reel 2500/Tape & Reel *The “T3” suffix refers to a 13 inch reel. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Individual devices are listed on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2006 1 October, 2006 − Rev. 9 Publication Order Number: 1SMB10CAT3/D 1SMB10CAT3 Series MAXIMUM RATINGS Rating Peak Power Dissipation (Note 1) @ TL = 25°C, Pulse Width = 1 ms DC Power Dissipation @ TL = 75°C Measured Zero Lead Length (Note 2) Derate Above 75°C Thermal Resistance from Junction−to−Lead DC Power Dissipation (Note 3) @ TA = 25°C Derate Above 25°C Thermal Resistance from Junction−to−Ambient Operating and Storage Temperature Range Symbol PPK PD Value 600 3.0 40 25 0.55 4.4 226 −65 to +150 Unit W W mW/°C °C/W W mW/°C °C/W °C RqJL PD RqJA TJ, Tstg Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 X 1000 ms, non−repetitive 2. 1″ square copper pad, FR−4 board 3. FR−4 board, using ON Semiconductor minimum recommended footprint, as shown in 403A case outline dimensions spec *Please see 1SMB5.0AT3 to 1SMB170AT3 for Unidirectional devices ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current IT VC VBR VRWM IR IPP I IR VRWM VBR VC IT V IPP Bi−Directional TVS http://onsemi.com 2 1SMB10CAT3 Series ELECTRICAL CHARACTERISTICS (Devices listed in bold, italic are ON Semiconductor Preferred devices.) VRWM (Note 4) Volts 10 11 12 13 14 15 16 17 18 20 22 24 26 28 30 33 36 40 43 45 48 51 54 58 60 64 75 Breakdown Voltage IR @ VRWM mA 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 VBR (Note 5) Volts Min 11.1 12.2 13.3 14.4 15.6 16.7 17.8 18.9 20.0 22.2 24.4 26.7 28.9 31.1 33.3 36.7 40.0 44.4 47.8 50.0 53.3 56.7 60.0 64.4 66.7 71.1 83.3 Nom 11.69 12.84 14.00 15.16 16.42 17.58 18.74 19.90 21.06 23.37 25.69 28.11 30.42 32.74 35.06 38.63 42.11 46.74 50.32 52.63 56.11 59.69 63.16 67.79 70.21 74.84 91.65 Max 12.27 13.5 14.7 15.9 17.2 18.5 19.7 20.9 22.1 24.5 27.0 29.5 31.9 34.4 36.8 40.6 44.2 49.1 52.8 55.3 58.9 62.7 66.32 71.18 73.72 78.58 92.07 @ IT mA 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 VC @ IPP (Note 6) VC Volts 17.0 18.2 19.9 21.5 23.2 24.4 26.0 27.6 29.2 32.4 35.5 38.9 42.1 45.4 48.4 53.3 58.1 64.5 69.4 72.2 77.4 82.4 87.1 93.6 96.8 103 121 IPP Amps 35.3 33.0 30.2 27.9 25.8 24.0 23.1 21.7 20.5 18.5 16.9 15.4 14.2 13.2 12.4 11.3 10.3 9.3 8.6 8.3 7.7 7.3 6.9 6.4 6.2 5.8 4.9 Ctyp (Note 7) pF 805 740 680 630 590 555 520 490 465 425 390 366 330 310 290 265 245 220 210 200 190 175 170 155 150 145 125 Device* 1SMB10CAT3, G 1SMB11CAT3, G 1SMB12CAT3, G 1SMB13CAT3, G 1SMB14CAT3, G 1SMB15CAT3, G 1SMB16CAT3, G 1SMB17CAT3, G 1SMB18CAT3, G 1SMB20CAT3, G 1SMB22CAT3, G 1SMB24CAT3, G 1SMB26CAT3, G 1SMB28CAT3, G 1SMB30CAT3, G 1SMB33CAT3, G 1SMB36CAT3, G 1SMB40CAT3, G 1SMB43CAT3, G 1SMB45CAT3, G 1SMB48CAT3, G 1SMB51CAT3, G 1SMB54CAT3, G 1SMB58CAT3, G 1SMB60CAT3, G 1SMB64CAT3, G 1SMB75CAT3, G Device Marking KXC KZC LEC LGC LKC LMC LPC LRC LTC LVC LXC LZC MEC MGC MKC MMC MPC MRC MTC MVC MXC MZC NEC NGC NKC NMC NRC 4. A transient suppressor is normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC or continuous peak operating voltage level. 5. VBR measured at pulse test current IT at an ambient temperature of 25°C. 6. Surge current waveform per Figure 2 and derate per Figure 3 of the General Data − 600 Watt at the beginning of this group. 7. Bias Voltage = 0 V, F = 1 MHz, TJ = 25°C *The “G” suffix indicates Pb−Free package available. http://onsemi.com 3 1SMB10CAT3 Series 100 PPK, PEAK POWER (kW) NONREPETITIVE PULSE WAVEFORM SHOWN IN FIGURE 2 10 tr ≤ 10 ms 100 VALUE (%) PEAK VALUE − IPP I HALF VALUE − PP 2 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAYS TO 50% OF IPP. 1 50 tP 0.1 0.1 ms 1 ms 10 ms 100 ms 1 ms 10 ms 0 0 1 2 t, TIME (ms) 3 4 5 tP, PULSE WIDTH Figure 1. Pulse Rating Curve Figure 2. Pulse Waveform 160 PEAK PULSE DERATING IN % OF PEAK POWER OR CURRENT @ T = 25° C A 140 1000 1SMB10CAT3G C, CAPACITANCE (pF) 1SMB18CAT3G 100 1SMB48CAT3G 1SMB75CAT3G 10 TJ = 25°C f = 1 MHz 1 10 BIAS VOLTAGE (V) 100 120 100 80 60 40 20 0 0 25 50 75 100 125 150 1 TA, AMBIENT TEMPERATURE (°C) Figure 3. Pulse Derating Curve Figure 4. Typical Junction Capacitance vs. Bias Voltage TYPICAL PROTECTION CIRCUIT Zin Vin LOAD VL http://onsemi.com 4 1SMB10CAT3 Series APPLICATION NOTES RESPONSE TIME In most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. In this situation, there is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. The capacitive effect is of minor importance in the parallel protection scheme because it only produces a time delay in the transition from the operating voltage to the clamp voltage as shown in Figure 4. The inductive effects in the device are due to actual turn-on time (time required for the device to go from zero current to full current) and lead inductance. This inductive effect produces an overshoot in the voltage across the equipment or component being protected as shown in Figure 5. Minimizing this overshoot is very important in the application, since the main purpose for adding a transient suppressor is to clamp voltage spikes. The SMB series have a very good response time, typically < 1 ns and negligible inductance. However, external inductive effects could produce unacceptable overshoot. Proper circuit layout, minimum lead lengths and placing the suppressor device as close as possible to the equipment or components to be protected will minimize this overshoot. Some input impedance represented by Zin is essential to prevent overstress of the protection device. This impedance should be as high as possible, without restricting the circuit operation. DUTY CYCLE DERATING The data of Figure 1 applies for non-repetitive conditions and at a lead temperature of 25°C. If the duty cycle increases, the peak power must be reduced as indicated by the curves of Figure 6. Average power must be derated as the lead or ambient temperature rises above 25°C. The average power derating curve normally given on data sheets may be normalized and used for this purpose. At first glance the derating curves of Figure 6 appear to be in error as the 10 ms pulse has a higher derating factor than the 10 ms pulse. However, when the derating factor for a given pulse of Figure 6 is multiplied by the peak power value of Figure 1 for the same pulse, the results follow the expected trend. http://onsemi.com 5 1SMB10CAT3 Series OVERSHOOT DUE TO INDUCTIVE EFFECTS Vin (TRANSIENT) VL VL V Vin (TRANSIENT) V Vin td tD = TIME DELAY DUE TO CAPACITIVE EFFECT t t Figure 5. Figure 6. 1 0.7 0.5 DERATING FACTOR 0.3 0.2 0.1 0.07 0.05 0.03 0.02 10 ms 0.01 0.1 0.2 0.5 1 2 5 10 D, DUTY CYCLE (%) 20 50 100 100 ms PULSE WIDTH 10 ms 1 ms Figure 7. Typical Derating Factor for Duty Cycle UL RECOGNITION The entire series has Underwriters Laboratory Recognition for the classification of protectors (QVGV2) under the UL standard for safety 497B and File #116110. Many competitors only have one or two devices recognized or have recognition in a non-protective category. Some competitors have no recognition at all. With the UL497B recognition, our parts successfully passed several tests including Strike Voltage Breakdown test, Endurance Conditioning, Temperature test, Dielectric Voltage-Withstand test, Discharge test and several more. Whereas, some competitors have only passed a flammability test for the package material, we have been recognized for much more to be included in their Protector category. http://onsemi.com 6 1SMB10CAT3 Series PACKAGE DIMENSIONS SMB CASE 403C−01 ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. D DIMENSION SHALL BE MEASURED WITHIN DIMENSION P. INCHES DIM MIN MAX A 0.160 0.180 B 0.130 0.150 C 0.075 0.095 D 0.077 0.083 H 0.0020 0.0060 J 0.006 0.012 K 0.030 0.050 P 0.020 REF S 0.205 0.220 MILLIMETERS MIN MAX 4.06 4.57 3.30 3.81 1.90 2.41 1.96 2.11 0.051 0.152 0.15 0.30 0.76 1.27 0.51 REF 5.21 5.59 S A D B C K P J H SOLDERING FOOTPRINT* 2.261 0.089 2.743 0.108 2.159 0.085 SCALE 8:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SURMETIC is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 7 1SMB10CAT3/D