Field Effect Transistor N-Channel, Enhancement
Mode
2N7002K
Features
•
•
•
•
•
•
•
•
Low On−Resistance
Low Gate Threshold Voltage
Low Input Capacitance
Fast Switching Speed
Low Input / Output Leakage
Ultra−Small Surface Mount Package
ESD HBM = 2000 V (Typical: 3000 V) as per JESD22 A114 and
ESD CDM = 2000 V as per JESD22 C101
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
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SOT−23 (TO−236)
CASE 318−08
MARKING DIAGRAM
7K M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Symbol
Parameter
Value
Unit
60
V
VDSS
Drain−Source Voltage
VDGR
Drain−Gate Voltage (RGS ≤ 1.0 MW)
60
V
VGSS
Gate−Source Voltage
±20
V
300
mA
ID
Drain Current
TJ
Operating Junction Temperature Range
−55 to +150
°C
Storage Temperature Range
−55 to +150
°C
Continuous
Pulsed
TSTG
1
7K
M
= Specific Device Code
= Date Code
FUNCTIONAL SCHEMATIC
D
800
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Symbol
PD
RqJA
Parameter
Value
G
S
Unit
Total Device Dissipation
350
mW
Derate Above TA = 25°C
2.8
mW/°C
Thermal Resistance, Junction−to−Ambient
(Note 1)
350
°C/W
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
1. Device mounted on FR−4 PCB, 1 inch x 0.85 inch x 0.062 inch;Minimum land
pad size.
© Semiconductor Components Industries, LLC, 2020
October, 2020 − Rev. 2
1
Publication Order Number:
2N7002K−FSC/D
2N7002K
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Max
Unit
OFF CHARACTERISTICS (Note 2)
BVDSS
IDSS
IGSS
Drain−Source Breakdown Voltage
VGS = 0 V, ID = 10 mA
60
−
V
Zero Gate Voltage Drain Current
VDS = 60 V, VGS = 0 V
−
1.0
mA
VDS = 60 V, VGS = 0 V, TJ = 125°C
−
500
VGS = ±20 V, VDS = 0 V
−
±10
mA
1.0
2.5
V
W
Gate−Body Leakage
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 mA
RDS(ON)
Static Drain−Source On−Resistance
VGS = 10 V, ID = 0.5 A
−
2
VGS = 4.5 V, ID = 200 mA
−
4
On−State Drain Current
VGS = 10 V, VDS = 7.5 V
1.5
−
A
Forward Transconductance
VDS = 10 V, ID = 0.2 A
200
−
mS
−
50
pF
ID(ON)
gFS
DYNAMIC CHARACTERISTICS
VDS = 25 V, VGS= 0 V, f = 1.0 MHz
Ciss
Input Capacitance
Coss
Output Capacitance
−
15
pF
Crss
Reverse Transfer Capacitance
−
6
pF
−
5
ns
−
30
ns
SWITCHING CHARACTERISTICS
tD(ON)
Turn−On Delay Time
tD(OFF)
Turn−Off Delay Time
VDD = 30 V, IDSS = 200 mA, RG = 10 W,
VGS = 10 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Short duration test pulse used to minimize self−heating effect.
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2
2N7002K
2.0
3.0
VGS = 10 V
RDS(on), DRAIN−SOURCE
ON−RESISTANCE (W)
ID, DRAIN−SOURCE CURRENT (A)
TYPICAL PERFORMANCE CHARACTERISTICS
5V
1.5
4V
1.0
3V
0.5
0.0
VGS = 3 V
2.5
4.5 V
5V
2.0
7V
1.0
8V
0
3.0
2
4
6
8
0.5
0.0
10
10 V
0.2
1.5
1.0
0
50
100
1.0
ID = 500 mA
0.5
0.0
150
ID = 50 mA
2
Vth, GATE−SOURCE THRESHOLD
VOLTAGE (V)
25°C
0.8
150°C
TJ = −25°C
125°C
0.4
75°C
0.2
3
4
5
4
5
6
7
8
9
10
Figure 4. On−Resistance Variation with
Gate−Source Voltage
1.0
VDS = 10 V
3
VGS, GATE−SOURCE VOLTAGE (V)
Figure 3. On−Resistance Variation with
Temperature
2
1.0
1.5
TJ, JUNCTION TEMPERATURE (°C)
0.6
0.8
2.0
2.0
0.5
−50
0.6
Figure 2. On−Resistance Variation
with Gate Voltage and Drain Current
VDS = 10 V
ID = 500 mA
2.5
0.4
ID, DRAIN−SOURCE CURRENT (A)
RDS(on), DRAIN−SOURCE
ON−RESISTANCE (W)
RDS(on), DRAIN−SOURCE
ON−RESISTANCE (W)
9V
2V
Figure 1. On−Region Characteristics
ID, DRAIN−SOURCE CURRENT (A)
6V
1.5
VDS, DRAIN−SOURCE VOLTAGE (V)
0.0
4V
2.0
VDS = VGS
1.8
ID = 1 mA
1.6
ID = 0.25 mA
1.4
1.2
1.0
−50
6
VGS, GATE−SOURCE VOLTAGE (V)
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Transfer Characteristics
Figure 6. Gate Threshold Variation with
Temperature
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3
150
VDS = 10 V
VGS, GATE−SOURCE VOLTAGE (V)
IS, REVERSE DRAIN CURRENT (mA)
2N7002K
100
TA = 150°C
25°C
10
−55°C
1
0.0
0.2
0.4
0.6
0.8
1.0
10
8
6
500 mA
280 mA
4
2
115 mA
0
0
0.1
0.2
VDS, DRAIN−SOURCE VOLTAGE (V)
0.3
0.4 0.5
0.6
0.7
0.8
0.9
1
Qg, GATE CHARGE
Figure 7. Reverse Drain Current Variation with
Diode Forward Voltage and Temperature
Figure 8. Gate Charge Characteristics
1
ID, DRAIN CURRENT (A)
0.5
100 ms
RDS(ON) LIMIT
1 ms
0.05
10ms
SINGLE PULSE
RqJA = 350°C/W
TA = 25°C
0.005
0.01
0.1
1
100 ms
1s
10 s
DC
10
100 200
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area
ORDERING INFORMATION
Part Number
Top Mark
Package
Shipping†
2N7002K
7K
SOT−23 3L
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AS
DATE 30 JAN 2018
SCALE 4:1
D
0.25
3
E
1
2
T
HE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
DIM
A
A1
b
c
D
E
e
L
L1
HE
T
L
3X b
L1
VIEW C
e
TOP VIEW
A
A1
SIDE VIEW
SEE VIEW C
c
MIN
0.89
0.01
0.37
0.08
2.80
1.20
1.78
0.30
0.35
2.10
0°
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.14
0.20
2.90
3.04
1.30
1.40
1.90
2.04
0.43
0.55
0.54
0.69
2.40
2.64
−−−
10 °
MIN
0.035
0.000
0.015
0.003
0.110
0.047
0.070
0.012
0.014
0.083
0°
INCHES
NOM
0.039
0.002
0.017
0.006
0.114
0.051
0.075
0.017
0.021
0.094
−−−
MAX
0.044
0.004
0.020
0.008
0.120
0.055
0.080
0.022
0.027
0.104
10°
GENERIC
MARKING DIAGRAM*
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT
XXXMG
G
1
3X
2.90
3X
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
0.90
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.95
PITCH
0.80
DIMENSIONS: MILLIMETERS
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 7:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 11:
STYLE 12:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. CATHODE
3. CATHODE−ANODE
3. ANODE
STYLE 15:
PIN 1. GATE
2. CATHODE
3. ANODE
STYLE 16:
PIN 1. ANODE
2. CATHODE
3. CATHODE
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
3. CATHODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. NO CONNECTION PIN 1. CATHODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
2. ANODE
3. GATE
3. ANODE
3. CATHODE−ANODE
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 22:
PIN 1. RETURN
2. OUTPUT
3. INPUT
STYLE 23:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 24:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 27:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
STYLE 28:
PIN 1. ANODE
2. ANODE
3. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
STYLE 8:
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
STYLE 13:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 25:
PIN 1. ANODE
2. CATHODE
3. GATE
STYLE 14:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 26:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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2N7002K