74ABT126CSJX

74ABT126 Quad Buffer with 3-STATE Outputs Features General Description ■ Non-inverting buffers The ABT126 contains four independent non-inverting buffers with 3-STATE outputs. ■ Output sink capability of 64mA, source capability of 32mA ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle Nondestructive hot insertion capability ■ ■ Disable time less than enable time to avoid bus contention Ordering Information Order Number 74ABT126CSC 74ABT126CSJ 74ABT126CMTC Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Function Table Inputs Output An Bn On H L L H H H L X Z H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial Pin Description Pin Names Description An, Bn Inputs On Outputs ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 74ABT126 — Quad Buffer with 3-STATE Outputs January 2008 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol TSTG Parameter Rating Storage Temperature –65°C to +150°C TA Ambient Temperature Under Bias –55°C to +125°C TJ Junction Temperature Under Bias –55°C to +150°C VCC VCC Pin Potential to Ground Pin –0.5V to +7.0V VIN Input Voltage(1) –0.5V to +7.0V IIN Input Current(1) –30mA to +5.0mA VO Voltage Applied to Any Output Disabled or Power-Off State –0.5V to 5.5V HIGH State –0.5V to VCC Current Applied to Output in LOW State (Max.) twice the rated IOL (mA) DC Latchup Source Current (Across Comm Operating Range) –300mA Over Voltage Latchup (I/O) 10V Note: 1. Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TA VCC ∆V / ∆t Parameter Rating Free Air Ambient Temperature –40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate Data Input 50mV/ns Enable Input ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 100mV/ns www.fairchildsemi.com 2 74ABT126 — Quad Buffer with 3-STATE Outputs Absolute Maximum Ratings Symbol Parameter VIH Input HIGH Voltage VCC Conditions Recognized HIGH Signal Min. Typ. Max. Units 2.0 V VIL Input LOW Voltage Recognized LOW Signal 0.8 V VCD Input Clamp Diode Voltage Min. IIN = –18mA –1.2 V VOH Output HIGH Voltage Min. IOH = –3mA 2.5 IOH = –32mA 2.0 VOL Output LOW Voltage Min. IOL = 64mA 0.55 V VIN = 2.7V 1 µA (2) V IIH Input HIGH Current Max. VIN = VCC 1 IBVI Input HIGH Current Breakdown Test Max. VIN = 7.0V 7 µA IIL Input LOW Current Max. VIN = 0.5V(2) –1 µA VID Input Leakage Test 0.0 IOZH Output Leakage Current 0–5.5V VOUT = 2.7V, OEn = 2.0V 10 µA IOZL Output Leakage Current 0–5.5V VOUT = 0.5V, OEn = 2.0V –10 µA IOS Output Short-Circuit Current Max. –275 mA ICEX Output HIGH Leakage Current Max. VIN = 0.0V IZZ Bus Drainage Test 0.0 IID = 1.9µA, All Other Pins Grounded VOUT = 0.0V –1 4.75 –100 V VOUT = VCC 50 µA VOUT = 5.5V, All Others GND 100 µA 50 µA ICCH Power Supply Current Max. All Outputs HIGH ICCL Power Supply Current Max. All Outputs LOW 15 mA ICCZ Power Supply Current Max. OEn = VCC, All Others at VCC or Ground 50 µA ICCT Additional ICC/Input ICCD VI = VCC – 2.1V 1.5 mA Outputs 3-STATE Enable Input VI = VCC – 2.1V 1.5 mA Outputs 3-STATE Data Input VI = VCC – 2.1V, All Others at VCC or Ground 50 µA Outputs OPEN, OEn = GND(3), One-Bit Toggling, 50% Duty Cycle 0.1 mA/ MHz Outputs Enabled Dynamic ICC No Load(2) Max. Max. Notes: 2. Guaranteed, but not tested. 3. For 8-bit toggling, ICCD < 0.8mA/MHz. ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 3 74ABT126 — Quad Buffer with 3-STATE Outputs DC Electrical Characteristics TA = +25°C, VCC = +5V, CL = 50pF Symbol Parameter Min. tPLH Propagation Delay, Data to Outputs tPHL Output Enable Time tPZH tPZL Output Disable Time tPHZ tPLZ Typ. TA = –40°C to +85°C VCC = 4.5V–5.5V CL = 50pF Max. Min. Max. Units 1.0 4.4 1.0 4.4 ns 1.0 4.6 1.0 4.6 1.0 6.5 1.0 6.5 1.0 6.5 1.0 6.5 1.0 5.8 1.0 5.8 1.0 5.5 1.0 5.5 ns ns Capacitance Symbol CIN COUT (4) Conditions TA = 25°C Parameter Typ. Units Input Capacitance VCC = 0V 5.0 pF Output Capacitance VCC = 5.0V 9.0 pF Note: 4. COUT is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 4 74ABT126 — Quad Buffer with 3-STATE Outputs AC Electrical Characteristics 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 5 74ABT126 — Quad Buffer with 3-STATE Outputs Physical Dimensions 74ABT126 — Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 6 74ABT126 — Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 7 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©1995 Fairchild Semiconductor Corporation 74ABT126 Rev. 1.4.0 www.fairchildsemi.com 8 74ABT126 — Quad Buffer with 3-STATE Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.