74ABT16374CMTD

Revised May 2005 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ Separate control logic for each byte ■ 16-bit version of the ABT374 ■ Edge-triggered D-type inputs ■ Buffered Positive edge-triggered clock ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability ■ Guaranteed latch-up protection Ordering Code: Order Number Package Number 74ABT16374CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Description 74ABT16374CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Name Description OEn 3-STATE Output Enable Input (Active LOW) CPn Clock Pulse Input (Active Rising Edge) D0–D15 Data Inputs O0–O15 3-STATE Outputs © 2005 Fairchild Semiconductor Corporation DS011668 www.fairchildsemi.com 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs March 1994 74ABT16374 Functional Description Truth Tables The ABT16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Inputs CP1   OE1 D0–D7 O0–O7 L H H L L L L L X (Previous) X H X Z Inputs Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) 2 Outputs   OE2 D8–D15 O8–O15 L H H L L L L L X (Previous) X H X Z CP2 H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.com Outputs Recommended Operating Conditions 65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) 40qC to 85qC 4.5V to 5.5V Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Voltage Applied to Any Output 50 mV/ns Enable Input 20 mV/ns Clock Input 100mV/ns in the Disabled or 0.5V to 5.5V 0.5V to VCC Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current: 350 mA OE Pin (Across Comm Operating Range) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. 500 mA Other Pins Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage 1.2 V Min IIN 18 mA VOH Output HIGH Voltage 2.5 V Min IOH 3 mA 2.0 V Min IOH 32 mA V Min IOL 64 mA PA Max VIN 2.7V (Note 3) VIN VCC PA Max VIN 7.0V VIN 0.5V (Note 3) VOL Output LOW Voltage IIH Input HIGH Current 2.0 V 0.55 1 1 IBVI Input HIGH Current Breakdown Test 7 IIL Input LOW Current 1 1 4.75 Recognized HIGH Signal Recognized LOW Signal PA Max V 0.0 VIN 0.0V IID 1.9 PA VID Input Leakage Test IOZH Output Leakage Current 10 PA 05.5V VOUT 2.7V; OE 2.0V IOZL Output Leakage Current 10 PA 05.5V VOUT 0.5V; OE 2.0V IOS Output Short-Circuit Current 275 mA Max VOUT 0.0V ICEX Output HIGH Leakage Current 50 PA Max VOUT V CC IZZ Bus Drainage Test 100 PA 0.0 VOUT 5.5V; All Others VCC or GND ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 62 mA Max All Outputs LOW ICCZ Power Supply Current 2.0 mA Max OE I CCT Additional ICC/Input 2.5 mA All Other Pins Grounded 100 Outputs Enabled Outputs 3-STATE 2.5 mA Outputs 3-STATE 2.5 mA VI Max VCC; All Others at VCC or GND VCC  2.1V Enable Input VI Data Input VI VCC  2.1V VCC  2.1V All Others at VCCor GND ICCD Dynamic ICC No Load mA/ (Note 3) 0.30 MHz Max Outputs Open OE GND, (Note 4) One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8-bit toggling, ICCD  0.8 mA/MHz. 3 www.fairchildsemi.com 74ABT16374 Absolute Maximum Ratings(Note 1) 74ABT16374 AC Electrical Characteristics (SSOP Package) 25qC TA Symbol Parameter VCC 5.0V CL 50 pF Min 40qC to 85qC TA V CC 4.5V to 5.5V CL Typ Max 50 pF Min Max fMAX Maximum Clock Frequency 150 tPLH Propagation Delay 1.8 tPHL CP to On 1.8 5.9 1.8 5.9 tPZH Output Enable Time 1.2 5.6 1.2 5.6 1.6 5.3 1.6 5.3 Output Disable Time 2.2 7.1 2.2 7.1 2.2 6.6 2.2 6.6 tPZL tPHZ tPLZ 150 6.2 Units MHz 1.8 6.2 ns ns ns AC Operating Requirements TA Symbol V CC Parameter CL Min tS(H) Setup Time, HIGH tS(L) tH(H) tH(L) tW(H) tW(L) 25qC TA 5.0V 40qC to 85qC VCC 50 pF 4.5V to 5.5V CL Max Min 1.1 1.1 or LOW Dn to CP 1.1 1.1 Hold Time, HIGH 1.3 1.3 or LOW Dn to CP 1.3 1.3 Pulse Width, CP 3.0 3.0 HIGH or LOW 3.0 3.0 Units 50 pF Max ns ns ns Capacitance Conditions Symbol Parameter CIN Input Capacitance COUT (Note 5) Output Capacitance Note 5: COUT is measured at frequency f www.fairchildsemi.com Typ Units 5.0 pF VCC 0V 11.0 pF VCC 5.0V 1 MHz, per MIL-STD-883, Method 3012. 4 (TA 25qC) 74ABT16374 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 5 www.fairchildsemi.com 74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6