74ABT244CMSA

Revised November 1999 74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The ABT244 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. ■ Non-inverting buffers ■ Output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability ■ Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT244CSC 74ABT244CSJ Package Number M20B M20D Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT244CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT244CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT244CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OE1, OE2 Output Enable Input I0–I7 Inputs O0–O7 Outputs (Active LOW) Truth Table OE1 I0–3 O0–3 OE2 I4–7 O4–7 H X Z H X Z L H H L H H L L L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance © 1999 Fairchild Semiconductor Corporation DS010992 www.fairchildsemi.com 74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs May 1992 74ABT244 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage V Min IOH = −3 mA V Min IOH = −32 mA VOL Output LOW Voltage 0.55 IIH Input HIGH Current 1 µA Max VIN = 2.7V (Note 4) IBVI Input HIGH Current Breakdown Test 7 µA Max IIL Input LOW Current −1 VID Input Leakage Test IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX IZZ 2.5 2.0 Recognized HIGH Signal Recognized LOW Signal IOL = 64 mA VIN = VCC 1 VIN = 7.0V VIN = 0.5V (Note 4) µA Max V 0.0 10 µA 0 − 5.5V −10 µA 0 − 5.5V −275 mA Max VOUT = 0.0V Output High Leakage Current 50 µA Max VOUT = VCC Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max OEn = VCC, ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs 3-STATE 2.5 mA Outputs 3-STATE 50 µA −1 4.75 VIN = 0.0V IID = 1.9 µA All Other Pins Grounded −100 VOUT = 2.7V; OEn = 2.0V VOUT = 0.5V; OEn = 2.0V All Others at VCC or Ground VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or Ground ICCD Dynamic ICC No Load mA/ (Note 4) 0.1 MHz Max Outputs OPEN OEn = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. www.fairchildsemi.com 2 74ABT244 DC Electrical Characteristics (SOIC package) Conditions Symbol Parameter Min Typ Max Units VCC CL = 50 pF, 0.5 0.8 V 5.0 TA = 25°C (Note 5) TA = 25°C (Note 5) RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL −1.3 −0.8 V 5.0 VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 TA = 25°C (Note 7) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.5 V 5.0 TA = 25°C (Note 6) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 6) 1.1 0.8 Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP package) Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min tPLH Propagation Delay 1.0 2.5 3.6 1.0 5.3 1.0 3.6 tPHL Data to Outputs 1.0 2.3 3.6 1.0 5.0 1.0 3.6 tPZH Output Enable 1.5 3.5 6.0 0.8 6.5 1.5 6.0 tPZL Time 1.5 3.6 6.0 1.2 7.9 1.5 6.0 tPHZ Output Disable 1.7 3.5 5.6 1.2 7.6 1.7 5.6 tPLZ Time 1.7 3.3 5.6 1.0 7.9 1.7 5.6 Units Max ns ns ns Extended AC Electrical Characteristics (SOIC package) Symbol TA−40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching 1 Output Switching 8 Outputs Switching Parameter (Note 8) Min (Note 9) Typ (Note 10) Max Min Max Min Max fTOGGLE Max Toggle Frequency tPLH Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.5 tPHL Data to Outputs 1.5 5.0 1.5 6.0 2.5 8.5 tPZH Output Enable Time 1.5 6.5 2.5 7.5 2.5 10.0 1.5 6.5 2.5 7.5 2.5 12.0 1.0 5.6 1.0 5.6 tPZL tPHZ tPLZ Output Disable Time Units 100 MHz (Note 11) (Note 11) ns ns ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet. 3 www.fairchildsemi.com 74ABT244 Skew Symbol Parameter tOSHL Pin to Pin Skew (Note 12) HL Transitions tOSLH Pin to Pin Skew (Note 12) LH Transitions tPS Duty Cycle (Note 16) LH–HL Skew tOST Pin to Pin Skew (Note 12) LH/HL Transitions tPV Device to Device Skew (Note 13) LH/HL Transitions TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 14) (Note 15) Max Max 0.8 1.8 ns 0.8 1.8 ns 1.0 2.5 ns 1.0 2.5 ns 1.5 3.0 ns Units Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST ). The specification is guaranteed but not tested. Note 13: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 15: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0V COUT (Note 17) Output Capacitance 9.0 pF VCC = 5.0V Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT244 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load AC Waveforms FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements FIGURE 6. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 4. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 6 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10