74ABT373CPC

74ABT373 Octal Transparent Latch with 3-STATE Outputs tm Features General Description ■ 3-STATE outputs for bus interfacing The ABT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. ■ Output sink capability of 64mA, source capability of 32mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50pF and 250pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High-impedance, glitch-free bus loading during entire power up and power down ■ Nondestructive, hot-insertion capability Ordering Information Package Number Package Description 74ABT373CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ABT373CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Order Number 74ABT373CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT373CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 Description D0–D7 Data Inputs LE Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) O0–O7 3-STATE Latch Outputs www.fairchildsemi.com 74ABT373 Octal Transparent Latch with 3-STATE Outputs March 2007 Truth Table The ABT373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Output LE OE Dn On H L H H H L L L L L X On (no change) X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance State Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 2 74ABT373 Octal Transparent Latch with 3-STATE Outputs Functional Description Symbol TSTG Parameter Rating Storage Temperature –65°C to +150°C TA Ambient Temperature Under Bias –55°C to +125°C TJ Junction Temperature Under Bias –55°C to +150°C VCC VCC Pin Potential to Ground Pin –0.5V to +7.0V VIN Input Voltage(1) –0.5V to +7.0V IIN Input Current(1) –30mA to +5.0mA VO Voltage Applied to Any Output Disabled or Power-Off State –0.5V to +5.5V HIGH State –0.5V to VCC Current Applied to Output in LOW State (Max.) twice the rated IOL (mA) DC Latchup Source Current Across Common Operating Range OE Pin –150mA Other Pins –500mA Over Voltage Latchup (I/O) 10V Note: 1. Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TA VCC ∆V / ∆t Parameter Rating Free Air Ambient Temperature –40°C to +85°C Supply Voltage +4.5V to +5.5V Minimum Input Edge Rate Data Input 50mV/ns Enable Input 20mV/ns ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 3 74ABT373 Octal Transparent Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VIH Input HIGH Voltage VCC Conditions Recognized HIGH Signal Min. Typ. Max. Units 2.0 V VIL Input LOW Voltage Recognized LOW Signal 0.8 V VCD Input Clamp Diode Voltage Min. IIN = –18mA –1.2 V VOH Output HIGH Voltage Min. IOH = –3mA 2.5 IOH = –32mA 2.0 VOL Output LOW Voltage Min. IOL = 64mA VIN = 2.7V (3) V 0.55 V 1 µA IIH Input HIGH Current Max. VIN = VCC 1 IBVI Input HIGH Current Breakdown Test Max. VIN = 7.0V 7 µA IIL Input LOW Current Max. VIN = 0.5V(3) –1 µA VID Input Leakage Test 0.0 IOZH Output Leakage Current 0–5.5V VOUT = 2.7V, OE = 2.0V 10 µA IOZL Output Leakage Current 0–5.5V VOUT = 0.5V, OE = 2.0V –10 µA IOS Output Short-Circuit Current Max. –275 mA ICEX Output HIGH Leakage Current Max. VIN = 0.0V IZZ Bus Drainage Test 0.0 IID = 1.9µA, All Other Pins Grounded VOUT = 0.0V –1 4.75 –100 V VOUT = VCC 50 µA VOUT = 5.5V, All Others GND 100 µA 50 µA ICCH Power Supply Current Max. All Outputs HIGH ICCL Power Supply Current Max. All Outputs LOW 30 mA ICCZ Power Supply Current Max. OE = VCC, All Others at VCC or Ground 50 µA ICCT Additional ICC/Input ICCD VI = VCC – 2.1V 2.5 mA Outputs 3-STATE Enable Input VI = VCC – 2.1V 2.5 mA Outputs 3-STATE Data Input VI = VCC – 2.1V, All Others at VCC or Ground 2.5 mA Outputs OPEN, LE = VCC, OE = GND(2), One-Bit Toggling, 50% Duty Cycle 0.12 mA/ MHz Outputs Enabled Dynamic ICC No Load(3) Max. Max. Notes: 2. For 8-bit toggling, ICCD < 0.8mA/MHz. 3. Guaranteed, but not tested. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 4 74ABT373 Octal Transparent Latch with 3-STATE Outputs DC Electrical Characteristics SOIC package. Symbol Parameter Conditions CL = 50pF, RL = 500Ω VCC Min. (4) Typ. Max. Units 0.4 0.8 V VOLP Quiet Output Maximum Dynamic VOL 5.0 TA = 25°C VOLV Quiet Output Minimum Dynamic VOL 5.0 TA = 25°C(4) –1.2 –0.8 V VOHV Minimum HIGH Level Dynamic Output Voltage 5.0 TA = 25°C(5) 2.5 3.0 V VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 TA = 25°C(6) 2.0 1.7 V VILD Maximum LOW Level Dynamic Input Voltage 5.0 TA = 25°C(6) 0.9 0.6 V Notes: 4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. 5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. 6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics SOIC and SSOP package. TA = +25°C, VCC = +5.0V, CL = 50pF Symbol Parameter TA = –55°C to +125°C, TA = –40°C to +85°C, VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V, CL = 50pF CL = 50pF Min. Typ. Max. Min. Max. Min. Max. Units Propagation Delay Dn to On 1.9 2.7 4.5 1.0 6.8 1.9 4.5 ns 1.9 2.8 4.5 1.0 7.0 1.9 4.5 2.0 3.1 5.0 1.0 7.7 2.0 5.0 tPHL Propagation Delay LE to On 2.0 3.0 5.0 1.5 7.7 2.0 5.0 tPZH Output Enable Time 1.5 3.1 5.3 1.0 6.7 1.5 5.3 1.5 3.1 5.3 1.5 7.2 1.5 5.3 2.0 3.6 5.4 1.7 8.0 2.0 5.4 2.0 3.4 5.4 1.0 7.0 2.0 5.4 tPLH tPHL tPLH tPZL tPHZ Output Disable Time tPLZ ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 ns ns ns www.fairchildsemi.com 5 74ABT373 Octal Transparent Latch with 3-STATE Outputs DC Electrical Characteristics SOIC and SSOP packages. TA = +25°C, VCC = +5.0V, CL = 50pF Symbol Parameter fTOGGLE Max Toggle Frequency Min. Typ. TA = –55°C to +125°C, TA = –40°C to +85°C, VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V CL = 50pF, CL = 50pF Max. Min. 100 Max. Min. 1.5 1.5 2.5 1.5 1.0 2.5 1.0 tH(L) Hold Time, HIGH or LOW, Dn to LE 1.0 2.5 1.0 tW(H) Pulse Width, LE HIGH 3.0 3.3 3.0 tS(L) tH(H) Units MHz Setup Time, HIGH or LOW, Dn to LE tS(H) Max. 100 2.5 1.5 ns ns ns Extended AC Electrical Characteristics SOIC package. TA = –40°C to +85°C, TA = –40°C to +85°C, VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V, CL = 50pF, CL = 250pF, TA = –40°C to +85°C, 8 Outputs VCC = 4.5V to 5.5V, 8 Outputs Switching(7) Switching(9) CL = 250pF(8) Symbol Min. Max. Min. Max. Min. Max. Units Propagation Delay, Dn to On 1.5 5.2 2.0 6.8 2.0 9.0 ns 1.5 5.2 2.0 6.8 2.0 9.0 1.5 5.5 2.0 7.5 2.0 9.5 tPHL Propagation Delay, LE to On 1.5 5.5 2.0 7.5 2.0 9.5 tPZH Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 1.5 6.2 2.0 8.0 2.0 10.5 1.0 5.5 1.0 5.5 tPLH tPHL tPLH Parameter tPZL tPHZ Output Disable Time tPZL (10) (10) ns ns ns Notes: 7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). 8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching only. 9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delay times are dominated by the RC network (500Ω, 250pF) on the output and has been excluded from the datasheet. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 6 74ABT373 Octal Transparent Latch with 3-STATE Outputs AC Operating Requirements SOIC package. Symbol Parameter TA = –40°C to +85°C, VCC = 4.5V–5.5V, CL = 50pF, 8 Outputs Switching(11) TA = –40°C to +85°C, VCC = 4.5V–5.5V, CL = 250pF, 8 Outputs Switching(12) Max. Max. Units (13) Pin to Pin Skew, HL Transitions 1.0 1.5 ns tOSLH(13) Pin to Pin Skew, LH Transitions 1.0 1.5 ns Duty Cycle, LH–HL Skew 1.4 3.5 ns Pin to Pin Skew, LH/HL Transitions 1.5 3.9 ns Device to Device Skew, LH/HL Transitions 2.0 4.0 ns tOSHL tPS(15) tOST (13) tPV(14) Notes: 11. This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50pF load capacitors in the standard AC load. 12. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). 13. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). This specification is guaranteed but not tested. 14. Propagation delay variation is for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. 15. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Capacitance Symbol CIN COUT (16) Conditions TA = 25°C Parameter Typ. Units Input Capacitance VCC = 0V 5 pF Output Capacitance VCC = 5.0V 9 pF Note: 16. COUT is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 7 74ABT373 Octal Transparent Latch with 3-STATE Outputs Skew *Includes jig and probe capacitance Figure 2. Test Input Signal Levels Figure 1. Standard AC Test Load Amplitude Rep. Rate tw tr tf 3.0V 1MHz 500ns 2.5ns 2.5ns Figure 3. Test Input Signal Requirements AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 6. 3-STATE Output HIGH and LOW Enable and Disable Times Figure 5. Propagation Delay, Pulse Width Waveforms Figure 7. Setup Time, Hold Time and Recovery Time Waveforms ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 8 74ABT373 Octal Transparent Latch with 3-STATE Outputs AC Loading 74ABT373 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 9 74ABT373 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 10 74ABT373 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 11 74ABT373 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 12 ® ACEx Across the board. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 ©1993 Fairchild Semiconductor Corporation 74ABT373 Rev. 1.4 www.fairchildsemi.com 13 74ABT373 Octal Transparent Latch with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.