74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
General Description
■ Edge-triggered D-type inputs
The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs
for bus-oriented applications. A buffered Clock (CP) and
Output Enable (OE) are common to all flip-flops.
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ Output sink capability of 64mA, source capability of
■
■
■
■
■
■
■
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down cycle
Nondestructive, hot-insertion capability
Ordering Information
Order Number
Package
Number
Package Description
74ABT374CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
74ABT374CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150,
5.3mm Wide
74ABT374CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
December 2007
Pin Descriptions
Pin Names
Functional Description
Description
D0–D7
Data Inputs
CP
Clock Pulse Input (Active Rising Edge)
OE
3-STATE Output Enable Input
(Active LOW)
O0–O7
3-STATE Outputs
Function Table
The ABT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs.
When OE is HIGH, the outputs are in a high impedance
state. Operation of the OE input does not affect the state
of the flip-flops.
Inputs
Internal Outputs
OE CP D
Q
O
Function
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
L
L
Z
Load
H
H
H
Z
Load
L
L
L
L
Data Available
L
H
H
H
Data Available
L
H
L
NC
NC
No Change in
Data
L
H
H
NC
NC
No Change in
Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
2
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
TSTG
Parameter
Rating
Storage Temperature
–65°C to +150°C
TA
Ambient Temperature Under Bias
–55°C to +125°C
TJ
Junction Temperature Under Bias
–55°C to +150°C
VCC
VCC Pin Potential to Ground Pin
–0.5V to +7.0V
VIN
Input Voltage(1)
–0.5V to +7.0V
IIN
Input Current(1)
–30mA to +5.0mA
VO
Voltage Applied to Any Output
Disabled or Power-Off State
–0.5V to 5.5V
HIGH State
–0.5V to VCC
Current Applied to Output in LOW State (Max.)
twice the rated IOL (mA)
DC Latchup Source Current Across Common Operating Range
OE Pin
–150mA
Other Pins
–500mA
Over Voltage Latchup (I/O)
10V
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA
VCC
∆V / ∆t
Parameter
Rating
Free Air Ambient Temperature
–40°C to +85°C
Supply Voltage
+4.5V to +5.5V
Minimum Input Edge Rate
Data Input
50mV/ns
Enable Input
20mV/ns
Clock Input
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
100mV/ns
www.fairchildsemi.com
3
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Absolute Maximum Ratings
Symbol
Parameter
VIH
Input HIGH Voltage
VCC
Conditions
Recognized HIGH Signal
Min.
Typ.
Max. Units
2.0
V
VIL
Input LOW Voltage
Recognized LOW Signal
0.8
V
VCD
Input Clamp Diode Voltage
Min.
IIN = –18mA
–1.2
V
VOH
Output HIGH Voltage
Min.
IOH = –3mA
2.5
IOH = –32mA
2.0
VOL
Output LOW Voltage
Min.
IOL = 64mA
0.55
V
VIN = 2.7V
1
µA
(3)
V
IIH
Input HIGH Current
Max.
VIN = VCC
1
IBVI
Input HIGH Current Breakdown
Test
Max.
VIN = 7.0V
7
µA
IIL
Input LOW Current
Max.
VIN = 0.5V(3)
–1
µA
VID
Input Leakage Test
0.0
IOZH
Output Leakage Current
0–5.5V VOUT = 2.7V, OE = 2.0V
10
µA
IOZL
Output Leakage Current
0–5.5V VOUT = 0.5V, OE = 2.0V
–10
µA
IOS
Output Short-Circuit Current
Max.
–275
mA
ICEX
Output HIGH Leakage Current
Max.
VOUT = VCC
50
µA
VOUT = 5.5V, All Others VCC or
GND
100
µA
VIN = 0.0V
IZZ
Bus Drainage Test
0.0
IID = 1.9µA, All Other Pins
Grounded
VOUT = 0.0V
–1
4.75
–100
V
ICCH
Power Supply Current
Max.
All Outputs HIGH
50
µA
ICCL
Power Supply Current
Max.
All Outputs LOW
30
mA
ICCZ
Power Supply Current
Max.
OE = VCC, All Others at VCC
or GND
50
µA
ICCT
Additional
ICC/Input
Max.
VI = VCC – 2.1V
2.5
mA
Outputs 3-STATE
Enable Input VI = VCC – 2.1V
2.5
mA
Outputs 3-STATE
Data Input VI = VCC – 2.1V,
All Others at VCC or GND
2.5
mA
Outputs OPEN, OE = GND(2),
One-Bit Toggling,
50% Duty Cycle
0.30
mA/
MHz
ICCD
Outputs Enabled
Dynamic ICC No Load(4)
Max.
Notes:
2. For 8-bit toggling, ICCD < 0.8mA/MHz.
3. Guaranteed, but not tested.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
4
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
DC Electrical Characteristics
SOIC package.
Symbol
VOLP
VOLV
Parameter
Conditions
CL = 50pF,
RL = 500Ω
VCC
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
Min.
Typ.
Max. Units
5.0
TA =
25°C(4)
5.0
TA =
25°C(4)
–1.3
–0.9
V
25°C(5)
2.5
3.0
V
2.0
1.6
V
VOHV
Minimum HIGH Level Dynamic Output
Voltage
5.0
TA =
VIHD
Minimum HIGH Level Dynamic Input
Voltage
5.0
TA = 25°C(6)
VILD
Maximum LOW Level Dynamic Input
Voltage
5.0
TA = 25°C(6)
0.5
1.3
0.8
0.8
V
V
Notes:
4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not
tested.
5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not
tested.
6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold
(VILD), 0V to threshold (VIHD). Guaranteed, but not tested.
AC Electrical Characteristics
SOIC and SSOP package.
TA = +25°C,
VCC = +5V,
CL = 50pF
Symbol
TA = –55°C to +125°C, TA = –40°C to +85°C,
VCC = 4.5V to 5.5V,
VCC = 4.5V to 5.5V,
CL = 50pF
CL = 50pF
Parameter
Min.
Typ.
fMAX
Maximum Clock
Frequency
150
200
tPLH
Propagation Delay
2.0
3.2
5.0
1.4
6.6
2.0
5.0
tPHL
CP to On
2.0
3.3
5.0
2.0
7.6
2.0
5.0
tPZH
Output Enable Time
1.5
3.1
5.3
0.8
5.7
1.5
5.3
1.5
3.1
5.3
1.5
7.2
1.5
5.3
tPZL
tPHZ
Output Disable Time
tPLZ
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
Max.
Min.
Max.
150
Min.
Max.
150
Units
MHz
1.5
3.6
5.4
1.3
7.2
1.5
5.4
1.5
3.4
5.4
1.0
7.0
1.5
5.4
ns
ns
ns
www.fairchildsemi.com
5
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
DC Electrical Characteristics
TA = +25°C
VCC = +5.0V
CL = 50pF
Symbol
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
Parameter
Min.
TA = –55°C to +125°C TA = –40°C to +85°C
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
CL = 50pF
CL = 50pF
Max.
Min.
Max.
Min.
Setup Time, HIGH or
LOW Dn to CP
1.5
2.5
1.0
1.5
2.5
1.5
Hold Time, HIGH or LOW
Dn to CP
1.0
2.5
1.0
1.0
2.5
1.0
Pulse Width, CP HIGH or
LOW
3.0
3.3
3.0
3.0
3.3
3.0
Max.
Units
ns
ns
ns
Extended AC Electrical Characteristics
SOIC package.
TA = –40°C to +85°C,
TA = –40°C to +85°C,
VCC = 4.5V to 5.5V,
VCC = 4.5V to 5.5V,
CL = 50pF,
TA = –40°C to +85°C,
CL = 250pF,
8 Outputs
VCC = 4.5V to 5.5V,
8 Outputs
Switching(7)
CL = 250pF(8)
Switching(9)
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
tPLH
Propagation
Delay CP to On
1.5
5.7
2.0
7.8
2.0
10.0
ns
1.5
5.7
2.0
7.8
2.0
10.0
Output Enable
Time
1.5
6.2
2.0
8.0
2.0
10.5
1.5
6.2
2.0
8.0
2.0
10.5
Output Disable
Time
1.0
5.5
1.0
5.5
tPHL
tPZH
tPZL
tPHZ
tPZL
(10)
(10)
ns
ns
Notes:
7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors
in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching
only.
9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load
capacitors in the standard AC load.
10. The 3-STATE delay Time is dominated by the RC network (500Ω, 250pF) on the output and has been excluded from
the datasheet.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
6
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
AC Operating Requirements
SOIC package.
Symbol
Parameter
TA = –40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
8 Outputs Switching(11)
TA = –40°C to +85°C
VCC = 4.5V–5.5V
CL = 250 pF
8 Outputs Switching(12)
Max.
Max.
Units
(13)
Pin to Pin Skew,
HL Transitions
1.0
1.8
ns
tOSLH(13)
Pin to Pin Skew,
LH Transitions
1.0
1.8
ns
tPS(12)
Duty Cycle, LH–HL Skew
1.8
4.3
ns
Pin to Pin Skew,
LH/HL Transitions
2.0
4.3
ns
Device to Device Skew,
LH/HL Transitions
2.5
4.6
ns
tOSHL
tOST
(13)
tPV(14)
Notes:
11. This specification is guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors
in place of the 50pF load capacitors in the standard AC load.
12. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same
pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the
guaranteed specification. This specification is guaranteed but not tested.
13. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate
outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH
(tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). This specification is guaranteed
but not tested.
14. Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This
specification is guaranteed but not tested.
15. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Capacitance
Symbol
CIN
COUT
(16)
Conditions
TA = 25°C
Parameter
Typ.
Units
Input Capacitance
VCC = 0V
5.0
pF
Output Capacitance
VCC = 5.0V
9.0
pF
Note:
16. COUT is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
7
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Skew(15)
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
AC Loading
*Includes jig and probe capacitance
Figure 1. Standard AC Test Load
Figure 2. VM = 1.5V
Input Pulse Requirements
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500ns
2.5ns
2.5ns
Figure 3. Test Input Signal Requirements
AC Waveforms
Figure 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
Figure 6. 3-STATE Output HIGH and
LOW Enable and Disable Times
Figure 5. Propagation Delay, Pulse Width Waveforms
Figure 7. Setup Time, Hold Time and
Recovery Time Waveforms
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
8
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.51
0.35
PIN ONE
INDICATOR
0.25
M
0.65
1.27
1.27
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
X 45°
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
GAGE PLANE
(R0.10)
0.10 C
0.30
0.10
0.25
8°
0°
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
(1.40)
DETAIL A
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
9
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
10
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
11
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
12
ACEx®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
PDP-SPM™
SyncFET™
®
Power220®
®
Power247
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
TinyBoost™
Programmable Active Droop™
TinyBuck™
®
QFET
TinyLogic®
QS™
TINYOPTO™
QT Optoelectronics™
TinyPower™
®
Quiet Series™
TinyPWM™
RapidConfigure™
TinyWire™
Fairchild®
SMART START™
Fairchild Semiconductor®
µSerDes™
®
SPM
FACT Quiet Series™
UHC®
STEALTH™
FACT®
Ultra FRFET™
SuperFET™
FAST®
UniFET™
SuperSOT™-3
FastvCore™
VCX™
®
®*
SuperSOT™-6
FlashWriter
SuperSOT™-8
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
FPS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com
13
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.