74ABT377CSCX

Revised November 1999 74ABT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. ■ Clock enable for address and data synchronization applications The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. ■ See ABT273 for master reset version ■ Eight edge-triggered D-type flip-flops ■ Buffered common clock ■ See ABT373 for transparent latch version ■ See ABT374 for 3-STATE version ■ Output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability ■ Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT377CSC 74ABT377CSJ Package Number M20B M20D Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Descriptions D0–D7 Data Inputs CE Clock Enable (Active LOW) CP Clock Pulse Input Q0–Q7 Data Outputs Truth Table Operating Mode Inputs CP Load “1” Load “0” Hold (Do Nothing)    X Output CE Dn Qn I h H I I L h X No Change H X No Change  H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition © 1999 Fairchild Semiconductor Corporation DS011550 www.fairchildsemi.com 74ABT377 Octal D-Type Flip-Flop with Clock Enable January 1993 74ABT377 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or Power-OFF State −0.5V to +4.75V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −500 mA DC Latchup Source Current (Across Comm Operating Range) Note 2: Either voltage limit or current limit is sufficient to protect inputs VCC + 4.5V Over Voltage Latchup DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC VIH Input HIGH Voltage V VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH Voltage V Min V Min µA Max µA Max µA Max V 0.0 −275 mA Max 2.5 2.0 VOL Output LOW Voltage IIH Input HIGH Current 0.55 1 1 IBVI Input HIGH Current 7 Breakdown Test IIL −1 Input LOW Current −1 Conditions Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA IOH = −3 mA IOH = −32 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA VID Input Leakage Test 4.75 IOS Output Short-Circuit Current −100 ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCT Maximum ICC/Input 1.5 mA Max Data Input VI = VCC − 2.1V 0.3 mA/ Max Outputs Open (Note 4) All Other Pins Grounded VOUT = 0.0V VI = VCC − 2.1V Outputs Enabled All Others at V CC or GND ICCD Dynamic ICC No Load MHz One bit Toggling, 50% Duty Cycle Note 3: Guaranteed but not tested. Note 4: For 8 bits toggling, ICCD < 0.5 mA/MHz. 3 www.fairchildsemi.com 74ABT377 Absolute Maximum Ratings(Note 1) 74ABT377 AC Electrical Characteristics (SOIC Package) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 150 200 Max Min tPLH Propagation Delay 2.2 6.0 2.2 6.0 tPHL CP to On 2.8 6.8 2.8 6.8 Units Max 150 MHz ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, HIGH 2.0 2.0 tS(L) or LOW Dn to CP 2.0 2.0 tH(H) Hold Time, HIGH 1.8 1.8 tH(L) or LOW Dn to CP 1.8 1.8 tS(H) Setup Time, HIGH 3.0 3.0 tS(L) or LOW CE to CP 3.0 3.0 tH(H) Hold Time, HIGH 1.0 1.0 tH(L) or LOW CE to CP 1.0 1.0 tW(H) Pulse Width, CP, 3.3 3.3 tW(L) HIGH or LOW 3.3 3.3 Max ns ns ns ns ns Capacitance (SOIC Package) (Note 5) Symbol Parameter Typ Units CIN Input Capacitance 5 pF VCC = 0V, TA = 25°C COUT (Note 5) Output Capacitance 9 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 Units Conditions 74ABT377 AC Loading *Includes jig and probe capacitance FIGURE 2. VM = 1.5V FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT377 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 6 74ABT377 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74ABT377 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74ABT377 Octal D-Type Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com