74ABT574CSCX

Revised March 2005 74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT574 is an octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. The device is functionally identical to the ABT374 but has broadside pinouts. ■ Inputs and outputs on opposite sides of package allowing easy interface with microprocessors ■ Useful as input or output port for microprocessors ■ Functionally identical to ABT374 ■ 3-STATE outputs for bus-oriented applications ■ Output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability Ordering Code: Order Number 74ABT574CSC 74ABT574CSJ Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT574CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT574CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names © 2005 Fairchild Semiconductor Corporation DS011511 Description D0–D7 Data Inputs CP Clock Pulse Input (Active Rising Edge) OE 3-STATE Output Enable Input (Active LOW) O0–O7 3-STATE Outputs www.fairchildsemi.com 74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs November 1992 74ABT574 Functional Description With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops. The ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. Function Table Inputs Internal Outputs Function OE CP D Q O H H or L L NC Z Hold H H or L H NC Z Hold H H L L     L L Z Load H H Z Load L L L Data Available H H H Data Available L H or L L NC NC No Change in Data L H or L H NC NC No Change in Data H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition NC No Change  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions 65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) 40qC to 85qC 4.5V to 5.5V Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input 50 mV/ns Enable Input Voltage Applied to Any Output 20 mV/ns Clock Input 100 mV/ns in the Disabled or 0.5V to 5.5V 0.5V to VCC Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. 500 mA DC Latchup Source Current Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage 1.2 V Min IIN 18 mA VOH Output HIGH Voltage 2.5 V Min IOH 3 mA 2.0 V Min IOH 32 mA IOL 64 mA VIN 2.7V (Note 3) VIN VCC VIN 7.0V VIN 0.5V (Note 3) 2.0 V VOL Output LOW Voltage 0.55 IIH Input HIGH Current 1 1 IBVI Input HIGH Current Breakdown Test 7 IIL Input LOW Current 1 1 4.75 Recognized HIGH Signal Recognized LOW Signal PA Max PA Max PA Max V 0.0 VIN 0.0V IID 1.9 PA VID Input Leakage Test IOZH Output Leakage Current 10 PA 0  5.5V VOUT 2.7V; OE 2.0V IOZL Output Leakage Current 10 PA 0  5.5V VOUT 0.5V; OE 2.0V IOS Output Short-Circuit Current 275 mA Max VOUT 0.0V All Other Pins Grounded 100 ICEX Output High Leakage Current 50 PA Max VOUT VCC IZZ Bus Drainage Test 100 PA 0.0 VOUT 5.5V; All Other GND ICCH Power Supply Current 50 PA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 PA Max OE VCC All Others at VCC or GND ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs 3-STATE 2.5 mA Outputs 3-STATE 2.5 mA VI Max V CC  2.1V VCC  2.1V Enable Input VI Data Input VI VCC  2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 3) 0.30 MHz Max Outputs Open, OE GND, One Bit Toggling (Note 4), 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8-bit toggling, ICCD  0.8 mA/MHz. 3 www.fairchildsemi.com 74ABT574 Absolute Maximum Ratings(Note 1) 74ABT574 DC Electrical Characteristics (SOIC Package) Symbol Parameter Min Typ Max Units VCC 0.7 1.0 V 5.0 VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL 1.5 1.1 V VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.6 V VILD Maximum LOW Level Dynamic Input Voltage V 1.2 0.8 Conditions CL 50 pF, RL 500: TA 25qC (Note 5) 5.0 TA 25qC (Note 5) 5.0 TA 25qC (Note 6) 5.0 TA 25qC (Note 7) 5.0 TA 25qC (Note 7) Note 5: Max number of outputs defined as (n). n  1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n  1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n  1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Package) 25qC TA Symbol Parameter CL 55qC to 125qC TA 5.0V VCC VCC 50 pF CL VCC 50 pF Min Typ 150 200 tPLH Propagation Delay 2.0 3.2 5.0 1.5 7.0 2.0 5.0 tPHL CP to On 2.0 3.3 5.0 1.5 7.4 2.0 5.0 tPZH Output Enable Time 1.5 3.1 5.3 1.0 6.5 1.5 5.3 1.5 3.1 5.3 1.0 7.2 1.5 5.3 1.5 3.6 5.4 1.0 7.2 1.5 5.4 1.5 3.4 5.4 1.0 6.7 1.5 5.4 tPHZ Output Disable Time Max 50 pF Maximum Clock Frequency tPLZ Min 4.5V to 5.5V CL fMAX tPZL Max 40qC to 85qC TA 4.5V to 5.5V Min 150 Units Max 150 MHz ns ns ns AC Operating Requirements TA Symbol Parameter 25qC VCC 5.0V CL 50 pF Min Max TA 55qC to 125qC VCC 4.5V to 5.5V CL Min 50 pF Max 40qC to 85qC TA VCC Min tS(H) Setup Time, HIGH 1.0 1.5 1.0 tS(L) or LOW Dn to CP 1.5 2.0 1.5 tH(H) Hold Time, HIGH 1.0 2.0 1.0 tH(L) or LOW Dn to CP 1.0 2.0 1.0 tW(H) Pulse Width, CP, 3.0 3.3 3.0 tW(L) HIGH or LOW 3.0 3.3 3.0 www.fairchildsemi.com 4 4.5V to 5.5V CL 50 pF Units Max ns ns ns 74ABT574 Extended AC Electrical Characteristics (SOIC Package) 40qC to 85qC TA VCC Symbol CL Parameter 40qC to 85qC TA 4.5V to 5.5V VCC 50 pF CL 8 Outputs Switching 40qC to 85qC TA 4.5V to 5.5V VCC 250 pF 4.5V to 5.5V CL (Note 9) 250 pF (Note 8) (Note 10) Min Max Min Max Min Max tPLH Propagation Delay 1.5 5.7 2.0 7.8 2.0 10.0 tPHL CP to On 1.5 5.7 2.0 7.8 2.0 10.0 tPZH Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 1.5 6.2 2.0 8.0 2.0 10.5 1.0 5.5 1.0 5.5 tPZL tPHZ Output Disable Time tPLZ Units 8 Outputs Switching (Note 11) (Note 11) ns ns ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE Delay Times are dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet. Skew (Note 12) (SOIC package) 40qC to 85qC TA VCC Symbol tOSHL Pin to Pin Skew (Note 14) HL Transitions tOSLH Pin to Pin Skew (Note 14) LH Transitions tPS Duty Cycle (Note 15) LH–HL Skew tOST Pin to Pin Skew (Note 14) LH/HL Transitions tPV Device to Device Skew (Note 16) LH/HL Transitions 40qC to 85qC VCC 50 pF CL Parameter TA 4.5V–5.5V CL 4.5V–5.5V 250 pF Units 8 Outputs Switching 8 Outputs Switching (Note 12) (Note 13) Max Max 1.0 1.8 ns 1.0 1.8 ns 1.8 4.3 ns 2.0 4.3 ns 2.5 4.6 ns Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Conditions Symbol Parameter CIN Input Capacitance COUT (Note 17) Output Capacitance Note 17: COUT is measured at frequency f Typ Units 5.0 pF V CC 0V 9.0 pF V CC 5.0V TA 25qC 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74ABT574 AC Loading *Includes jig and probe capacitance FIGURE 2. VM FIGURE 1. Standard AC Test Load 1.5V Input Pulse Requirements Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 7 www.fairchildsemi.com 74ABT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74ABT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com 74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10