74ABT652CMSAX

Revised January 1999 74ABT652 Octal Transceivers and Registers with 3-STATE Outputs General Description The ABT652 consists of bus transceiver circuits with Dtype flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. ■ A and B output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed latchup protection Features ■ Independent registers for A and B buses ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Multiplexed real-time and stored data ■ Nondestructive hot insertion capability Ordering Code: Order Number Package Number 74ABT652CSC M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT652CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT652CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for SOIC, SSOP and TSSOP © 1999 Fairchild Semiconductor Corporation Pin Names A0–A7 DS011512.prf Description Data Register A Inputs/3-STATE Outputs B0–B7 Data Register B Inputs/3-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs www.fairchildsemi.com 74ABT652 Octal Transceivers and Registers with 3-STATE Outputs November 1992 74ABT652 Truth Table Inputs Inputs/Outputs (Note 1) OEBA CPAB CPBA H H or L     H or L OEAB L L H X H H H L X L L L L H or L X     H or L SAB A0 thru A7 SBA X X X X Input Operating Mode B0 thru B7 Input Isolation Store A and B Data X X Input Not Specified Store A, Hold B X X Input Output X X Not Specified Input Store A in Both Registers Hold A, Store B X X Output Input Store B in Both Registers X X L Output Input Real-Time B Data to A Bus Input Output L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition  Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. Functional Description Data on the A or B data bus, or both, can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ABT652. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 OEAB OEBA L L Note B: Real-Time Transfer Bus A to Bus B CPAB CPBA SAB SBA X X X OEAB OEBA L H Note C: Storage OEAB OEBA X H L X L H     74ABT652 Note A: Real-Time Transfer Bus B to Bus A H CPAB CPBA SAB SBA X X L X Note D: Transfer Storage Data to A or B CPAB CPBA SAB SBA X X X X X X X X OEAB OEBA H L CPAB CPBA SAB SBA H or L H or L H H FIGURE 1. 3 www.fairchildsemi.com 74ABT652 Absolute Maximum Ratings(Note 2) Over Voltage Latchup (I/O) Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C Recommended Operating Conditions VCC Pin Potential to Ground Pin −0.5V to +7.0V Free Air Ambient Temperature Input Voltage (Note 3) −0.5V to +7.0V Supply Voltage Input Current (Note 3) −30 mA to +5.0 mA in the Disable −0.5V to +5.5V Data Input 50 mV/ns Enable Input 20 mV/ns 100 mV/ns Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 3: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) in LOW State (Max) +4.5V to +5.5V Clock Input −0.5V to VCC in the HIGH State −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) Voltage Applied to Any Output or Power-Off State 10V −500 mA DC Latchup Source Current DC Electrical Characteristics Symbol Parameter Min Typ Max VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH 2.5 V Min Voltage 2.0 VOL Output LOW Voltage VID Input Leakage Test 2.0 Units VIH V Conditions Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −32 mA, (An, Bn) 0.55 4.75 V Min V 0.0 IOL = 64 mA, (An, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded IIH Input HIGH Current 1 µA Max VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) 1 IBVI Input HIGH Current Breakdown Test 7 µA Max VIN = 7.0V (Non-I/O Pins) IBVIT Input HIGH Current Breakdown Test (I/O) 100 µA Max VIN = 5.5V (An, B n) IIL Input LOW Current −1 µA Max −1 IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) 10 µA 0V–5.5V VOUT = 2.7V (An, Bn); −10 µA 0V–5.5V VOUT = 0.5V (An, Bn); −275 mA Max VOUT = 0V (An, Bn) Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn) IZZ Bus Drainage Test 100 µA 0.0V VOUT = 5.5V (An, Bn); All Others GND ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max Outputs 3-STATE; ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V ICCD Dynamic ICC 0.18 mA/MHz Max OEBA = 2.0V and OEAB = GND = 2.0V OEBA = 2.0V and OEAB = GND = 2.0V −100 All others at VCC or GND All others at VCC or GND No Load Outputs Open (Note 5) OEAB = OEBA = GND (Note 6) One bit toggling, 50% duty cycle Note 4: Guaranteed but not tested. Note 5: For 8 outputs toggling, ICCD < 1.4 mA/MHz. Note 6: Guaranteed, but not tested. www.fairchildsemi.com 4 (SOIC package) Symbol Parameter Min Typ Max Units VCC 0.6 0.8 Conditions CL = 50 pF, RL = 500Ω TA = 25°C (Note 7) VOLP Quiet Output Maximum Dynamic VOL V 5.0 VOLV Quiet Output Minimum Dynamic VOL −1.2 −0.9 V 5.0 TA = 25°C (Note 7) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 8) VIHD Minimum HIGH Level Dynamic Input Voltage 2.2 VILD Maximum LOW Level Dynamic Input Voltage 1.8 0.8 0.4 V 5.0 TA = 25°C (Note 9) V 5.0 TA = 25°C (Note 9) Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 9: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Package) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max fmax Max Clock Frequency 200 tPLH Propagation Delay 1.7 3.0 4.9 1.7 4.9 tPHL Clock to Bus 1.7 3.4 4.9 1.7 4.9 tPLH Propagation Delay 1.5 2.6 4.5 1.5 4.5 tPHL Bus to Bus 1.5 3.0 4.5 1.5 4.5 tPLH Propagation Delay 1.5 3.0 5.0 1.5 5.0 tPHL SBA or SAB to An to Bn 1.5 3.4 5.0 1.5 5.0 tPZH Enable Time 1.5 3.3 5.5 1.5 5.5 tPZL OEBA or OEAB to An or Bn 1.5 3.7 5.5 1.5 5.5 tPHZ Disable Time 1.5 3.7 6.0 1.5 6.0 tPLZ OEBA or OEAB to An or Bn 1.5 3.3 6.0 1.5 6.0 200 5 Units MHz ns ns ns ns ns www.fairchildsemi.com 74ABT652 DC Electrical Characteristics 74ABT652 AC Operating Requirements Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min tS(H) Setup Time, HIGH tS(L) or LOW Bus to Clock tH(H) Hold Time, HIGH tH(L) or LOW Bus to Clock tW(H) Pulse Width, tW(L) HIGH or LOW Max Min Units Max 1.5 1.5 ns 1.0 1.0 ns 3.0 3.0 ns Extended AC Electrical Characteristics (SOIC package): Symbol Parameter TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching 1 Output Switching 8 Outputs Switching (Note 10) (Note 11) (Note 12) Min Max Min Max Min Max tPLH Propagation Delay 1.5 5.5 2.0 7.5 2.5 10.0 tPHL Clock to Bus 1.5 5.5 2.0 7.5 2.5 10.0 tPLH Propagation Delay 1.5 6.0 2.0 7.0 2.5 9.5 tPHL Bus to Bus 1.5 6.0 2.0 7.0 2.5 9.5 tPLH Propagation Delay 1.5 6.0 2.0 7.5 2.5 10.0 tPHL SBA or SAB to An or Bn 1.5 6.0 2.0 7.5 2.5 10.0 tPZH Output Enable Time 1.5 6.0 2.0 8.0 2.5 11.5 2.0 8.0 2.5 11.5 tPZL OEBA or OEAB to An or Bn 1.5 6.0 tPHZ Output Disable Time 1.5 6.0 tPLZ OEBA or OEAB to An or Bn 1.5 6.0 (Note 13) Units (Note 13) ns ns ns ns ns Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. www.fairchildsemi.com 6 74ABT652 Skew (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 16) (Note 17) Max Max 1.3 2.5 ns 1.0 2.0 ns 2.0 4.0 ns 2.0 4.0 ns 2.5 4.5 ns Parameter tOSHL Pin to Pin Skew (Note 14) HL Transitions tOSLH Pin to Pin Skew (Note 14) LH Transitions tPS Duty Cycle (Note 18) LH–HL Skew tOST Pin to Pin Skew (Note 14) LH/HL Transitions tPV Device to Device Skew (Note 15) LH/HL Transitions Units Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-toLOW (tOST). This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 17: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 18: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Capacitance Symbol Parameter Typ Units Conditions (TA = 25°C) CIN Input Capacitance 5.0 pF V CC = 0V (non I/O pins) CI/O (Note 19) I/O Capacitance 11.0 pF V CC = 5.0V (An, Bn) Note 19: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883D, Method 3012. 7 www.fairchildsemi.com 74ABT652 AC Loading *Includes jig and probe capacitance FIGURE 2. Standard AC Test Load FIGURE 3. Test Input Signal Levels Input Pulse Requirements Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 4. Test Input Signal Requirements AC Waveforms FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 6. Propagation Delay, Pulse Width Waveforms FIGURE 8. Setup Time, Hold Time www.fairchildsemi.com and Recovery Time Waveforms 8 74ABT652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 9 www.fairchildsemi.com 74ABT652 Octal Transceivers and Registers with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.