74AC377SJX

74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable Features General Description ■ ICC reduced by 50% The AC/ACT377 has eight edge-triggered, D-type flipflops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. ■ Ideal for addressable register applications ■ Clock enable for address and data synchronization ■ ■ ■ ■ ■ ■ ■ applications Eight edge-triggered D-type flip-flops Buffered common clock Outputs source/sink 24mA See 273 for master reset version See 373 for transparent latch version See 374 for 3-STATE version ACT377 has TTL-compatible inputs The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Ordering Information Package Number Package Description 74AC377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Order Number 74AC377MTC MTC20 74ACT377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT377MTC 74ACT377PC MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. FACT™ is a trademark of Fairchild Semiconductor Corporation. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable January 2008 Pin Descriptions Pin Names Description D0–D7 Data Inputs CE Clock Enable (Active LOW) Q0–Q7 Data Outputs CP Clock Pulse Input Logic Symbols IEEE/IEC Mode Select-Function Table Inputs Outputs CE Dn Qn Load ‘1' L H H Load ‘0' L L L Operating Mode CP Hold (Do Nothing) X H X No Change H X No Change H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 2 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Connection Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 3 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Logic Diagram Symbol VCC IIK Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Diode Current VI = –0.5V –20mA VI = VCC + 0.5V +20mA VI DC Input Voltage IOK DC Output Diode Current –0.5V to VCC + 0.5V VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.5V IO DC Output Source or Sink Current ±50mA ICC or IGND DC VCC or Ground Current per Output Pin ±50mA TSTG Storage Temperature –65°C to +150°C TJ Junction Temperature 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V VI Input Voltage VO Output Voltage TA Operating Temperature ∆V / ∆t Rating 0V to VCC 0V to VCC –40°C to +85°C Minimum Input Edge Rate, AC Devices: 125mV/ns VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V ∆V / ∆t Minimum Input Edge Rate, ACT Devices: 125mV/ns VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 4 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V Maximum LOW Level Input Voltage VOH Units 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 2.56 2.46 3.86 3.76 4.86 4.76 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 0.36 0.44 0.36 0.44 0.36 0.44 ±0.1 ±1.0 µA 4.5 3.0 4.5 VOUT = 0.1V or VCC – 0.1V 5.5 Minimum HIGH Level Output Voltage Guaranteed Limits 1.5 5.5 VIL Typ. TA = –40°C to +85°C 3.0 3.0 IOUT = –50µA VIN = VIL or VIH, V V V IOH = –12mA 4.5 VIN = VIL or VIH, IOH = –24mA 5.5 VIN = VIL or VIH, IOH = VOL Maximum LOW Level Output Voltage 3.0 3.0 –24mA(1) IOUT = 50µA VIN = VIL or VIH, V IOL = 12mA 4.5 VIN = VIL or VIH, IOL = 24mA 5.5 VIN = VIL or VIH, IOL = 24mA(1) IIN(3) Maximum Input Leakage Current 5.5 VI = VCC, GND IOLD Minimum Dynamic Output Current(2) 5.5 VOLD = 1.65V Max. 75 mA VOHD = 3.85V Min. –75 mA Maximum Quiescent Supply Current 5.5 40.0 µA IOHD ICC (3) VIN = VCC or GND 4.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 5 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter VCC (V) TA = +25°C Conditions Typ. TA = –40°C to +85°C Guaranteed Limits VOUT = 0.1V or VCC – 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC – 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = –50µA 4.49 4.4 4.4 Minimum HIGH Level Input Voltage 4.5 Maximum LOW Level Input Voltage 4.5 Minimum HIGH Level Output Voltage 5.5 5.5 4.5 5.49 VIN = VIL or VIH, 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 Units V V V IOH = –24mA 5.5 VIN = VIL or VIH, IOH = –24mA(4) VOL Maximum LOW Level Output Voltage 4.5 IOUT = 50µA 0.001 5.5 4.5 0.001 VIN = VIL or VIH, 0.1 0.1 0.36 0.44 0.36 0.44 ±0.1 ± 1.0 V IOL = 24mA 5.5 VIN = VIL or VIH, IOL = 24mA(4) IIN Maximum Input Leakage Current 5.5 VI = VCC, GND µA ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 1.5 mA IOLD Minimum Dynamic Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA VOHD = 3.85V Min. –75 mA Maximum Quiescent Supply Current 5.5 40.0 µA IOHD ICC 0.6 VIN = VCC or GND 4.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 6 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable DC Electrical Characteristics for ACT TA = +25°C Symbol fMAX tPLH tPHL Parameter VCC (V)(6) Min. Typ. TA = –40°C to +85°C Max. Min. Max. Maximum Clock Frequency 3.3 90 125 75 5.0 140 175 125 Propagation Delay, 3.3 3.0 8.0 13.0 1.5 14.0 CP to Qn 5.0 2.0 6.0 9.0 1.5 10.0 Propagation Delay, 3.3 3.5 8.5 13.0 2.0 14.5 CP to Qn 5.0 2.5 6.5 10.0 1.5 11.0 Units MHz ns ns Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V AC Operating Requirements for AC TA = +25°C, CL = 50pF TA = –40°C to +85°C, CL = 50pF Symbol Parameter VCC (V)(7) Typ. tS Setup Time, HIGH or LOW, Dn to CP 3.3 3.5 5.5 6.0 5.0 2.5 4.0 4.5 Hold Time, HIGH or LOW, Dn to CP 3.3 –2.0 0 0 5.0 –1.0 1.0 1.0 Setup Time, HIGH or LOW, CE to CP 3.3 4.0 6.0 7.5 5.0 2.5 4.0 4.5 Hold Time, HIGH or LOW, CE to CP 3.3 –3.5 0 0 5.0 –2.0 1.0 1.0 CP Pulse Width, HIGH or LOW 3.3 3.5 5.5 6.0 5.0 2.5 4.0 4.5 tH tS tH tW Guaranteed Minimum Units ns ns ns ns ns Note: 7. Voltage range 3.3 is 3.0V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 7 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable AC Electrical Characteristics for AC TA = +25°C, CL = 50pF Symbol Parameter VCC (V)(8) Min. Typ. TA = –40°C to +85°C, CL = 50pF Max. Min. Max. Units fMAX Maximum Clock Frequency 5.0 140 175 125 MHz tPLH Propagation Delay, CP to Qn 5.0 3.0 6.5 9.0 2.5 10.0 ns tPHL Propagation Delay, CP to Qn 5.0 3.5 7.0 10.0 2.5 11.0 ns Note: 8. Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT TA = +25°C, CL = 50pF TA = –40°C to +85°C, CL = 50pF Symbol Parameter VCC (V)(9) Typ. tS Setup Time, HIGH or LOW, Dn to CP 5.0 2.5 4.5 5.5 ns tH Hold Time, HIGH or LOW, Dn to CP 5.0 –1.0 1.0 1.0 ns tS Setup Time, HIGH or LOW, CE to CP 5.0 2.5 4.5 5.5 ns tH Hold Time, HIGH or LOW, CE to CP 5.0 –1.0 1.0 1.0 ns tW CP Pulse Width, HIGH or LOW 5.0 2.0 4.0 4.5 ns Typ. Units Guaranteed Minimum Units Note: 9. Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Conditions CIN Input Capacitance VCC = OPEN 4.5 pF CPD Power Dissipation Capacitance VCC = 5.0V 90.0 pF ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 8 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable AC Electrical Characteristics for ACT 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 9 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Physical Dimensions 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 10 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Physical Dimensions (Continued) Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 11 26.92 24.89 7.11 6.09 PIN #1 (0.97) 1.78 1.14 2.54 0.36 0.56 .001[.025] 3.43 3.17 5.33 MAX 7° TYP 7.87 7° TYP 3.55 3.17 0.38 MIN 7.62 10.92 MAX 0.20 0.35 C NOTES: Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 12 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable Physical Dimensions (Continued) ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ©1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Rev. 1.6.1 www.fairchildsemi.com 13 74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.