DATA SHEET
www.onsemi.com
Hex Inverter
74AC04, 74ACT04
SOIC−14 NB
CASE 751A−03
14
1
General Description
1
Features
•
•
•
•
SOIC14
CASE 751EF
14
The AC/ACT04 contains six inverters.
ICC Reduced by 50% On 74AC Only
Outputs Source/Sink 24 mA
ACT04 has TTL−Compatible Inputs
These are Pb−Free Devices
1
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
Value
Unit
VCC
−0.5 to +7.0
V
DC Input Diode Current
VI = −0.5 V
VI = VCC + 0.5 V
IIK
DC Input Voltage
VI
DC Output Diode Current
VO = −0.5 V
VO = VCC + 0.5 V
IOK
DC Output Voltage
VO
−0.5 to
VCC + 0.5
V
DC Output Source or Sink Current
IO
±50
mA
ICC or IGND
±50
mA
Storage Temperature
TSTG
−65 to +150
°C
Junction Temperature
PDIP
TJ
140
°C
DC VCC or Ground Current
per Output Pin
TSSOP−14 WB
CASE 948G
14
TSSOP−14 WB
CASE 948G−01
14
1
mA
−20
+20
MARKING DIAGRAM
−0.5 to
VCC + 0.5
V
14
AC(T)04
AWLYWW
mA
−20
+20
1
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
AC04, ACT04
A
WL
Y
WW
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
MARKING DIAGRAM
14
AC(T)
04
ALYWG
G
1
AC04, ACT04
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
© Semiconductor Components Industries, LLC, 2005
December, 2021 − Rev. 2
1
Publication Order Number:
74ACT04/D
74AC04, 74ACT04
ORDERING INFORMATION
Order Number
Package Number
74AC04SC
Package Description
M14A
74AC04MTC
MTC14
74ACT04SC
M14A
74ACT04MTC
14−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−012, 0.150” Narrow
14−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide
14−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−012, 0.150” Narrow
MTC14
14−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide
NOTES: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. All packages are lead free per
JEDEC: J−STD−020B standard.
IEEE/IEC
Figure 2. Logic Symbol
Figure 1. Connection Diagram
PIN DESCRIPTION
Pin
Description
An
Inputs
On
Outputs
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
AC
ACT
Min
Max
2.0
4.5
6.0
5.5
Unit
V
VI
Input Voltage
0
VCC
V
VO
Output Voltage
0
VCC
V
TA
Operating Temperature
−40
+85
°C
DV / Dt
Minimum Input Edge Rate, AC Devices:
VIN from 30% to 70% of VCC,VCC at 3.3 V, 4.5 V, 5.5 V
125
mV/ns
DV / Dt
Minimum Input Edge Rate, ACT Devices:
VIN from 0.8 V to 2.0 V, VCC at 4.5 V, 5.5 V
125
mV/ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
2
74AC04, 74ACT04
DC ELECTRICAL CHARACTERISTICS FOR AC
TA = +255C
Symbol
VIH
Parameter
Minimum HIGH Level
Input Voltage
VCC(V)
3.0
Conditions
VOUT = 0.1 V
or VCC − 0.1 V
Maximum LOW Level
Input Voltage
2.1
2.1
2.25
3.15
3.15
2.75
3.85
3.85
1.5
0.9
0.9
2.25
1.35
1.35
2.75
1.65
1.65
2.99
2.9
2.9
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
4.5
3.0
4.5
VOUT = 0.1 V
or VCC − 0.1 V
5.5
VOH
VOL
IIN
(Note 3)
IOLD
IOHD
ICC
(Note 3)
Minimum HIGH Level
Output Voltage
Maximum LOW Level
Output Voltage
TA = −405C to +855C
Guaranteed Limits
1.5
5.5
VIL
Typ
3.0
IOUT = −50 mA
3.0
VIN = VIL or VIH,
IOH = −12 mA
−
2.56
2.46
4.5
IOH = −24 mA
−
3.86
3.76
5.5
IOH = −24 mA (Note 1)
−
4.86
4.76
3.0
IOUT = 50 mA
0.002
0.1
0.1
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
Unit
V
V
V
V
3.0
VIN = VIL or VIH,
IOL = 12 mA
−
0.36
0.44
4.5
IOL = 24 mA
−
0.36
0.44
5.5
IOL = 24 mA (Note 1)
−
0.36
0.44
Maximum Input
Leakage Current
5.5
VI = VCC, GND
−
±0.1
±1.0
mA
Minimum Dynamic
Output Current (Note 2)
5.5
VOLD = 1.65 V Max.
−
−
75
mA
5.5
VOHD = 3.85 V Min.
−
−
−75
mA
Maximum Quiescent
Supply Current
5.5
VIN = VCC or GND
−
2.0
20.0
mA
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0 ms, one output loaded at a time.
3. IIN and ICC at 3.0 V are guaranteed to be less than or equal to the respective limit at 5.5 V VCC.
www.onsemi.com
3
74AC04, 74ACT04
DC ELECTRICAL CHARACTERISTICS FOR ACT
TA = +255C
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC(V)
Minimum HIGH Level
Input Voltage
4.5
Maximum LOW Level
Input Voltage
4.5
Minimum HIGH Level
Output Voltage
4.5
Maximum LOW Level
Output Voltage
5.5
5.5
Conditions
Typ
TA = −405C to +855C
Guaranteed Limits
VOUT = 0.1 V
or VCC − 0.1 V
1.5
2.0
2.0
1.5
2.0
2.0
VOUT = 0.1 V
or VCC − 0.1 V
1.5
0.8
0.8
1.5
0.8
0.8
IOUT = −50 mA
4.49
4.4
4.4
5.49
5.4
5.4
5.5
4.5
VIN = VIL or VIH
IOH = −24 mA
−
3.86
3.76
5.5
IOH = −24 mA (Note 4)
−
4.86
4.76
4.5
IOUT = 50 mA
0.001
0.1
0.1
0.001
0.1
0.1
5.5
Unit
V
V
V
V
4.5
VIN = VIL or VIH
IOL = 24 mA
−
0.36
0.44
5.5
IOL = 24 mA (Note 4)
−
0.36
0.44
Maximum Input
Leakage Current
5.5
VI = VCC, GND
−
±0.1
±1.0
mA
ICCT
Maximum ICC/Input
5.5
VI = VCC − 2.1 V
0.6
−
1.5
mA
IOLD
Minimum Dynamic
Output Current (Note 5)
5.5
VOLD = 1.65 V Max.
−
−
75
mA
5.5
VOHD = 3.85 V Min.
−
−
−75
mA
Maximum Quiescent
Supply Current
5.5
VIN = VCC or GND
−
4.0
40.0
mA
IIN
IOHD
ICC
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0 ms, one output loaded at a time.
www.onsemi.com
4
74AC04, 74ACT04
AC ELECTRICAL CHARACTERISTICS FOR AC
TA = +25°C, CL = 50 pF
Symbol
tPLH
tPHL
Parameter
TA = −40°C to +85°C, CL = 50 pF
VCC(V) (Note 6)
Min
Typ
Max
Min
Max
Unit
3.3
1.5
4.5
9.0
1.0
10.0
ns
5.0
1.5
4.0
7.0
1.0
7.5
3.3
1.5
4.5
8.5
1.0
9.5
5.0
1.5
3.5
6.5
1.0
7.0
Propagation Delay
Propagation Delay
ns
6. Voltage range 3.3 is 3.3 V + 0.3 V. Voltage range 5.0 is 5.0 V + 0.5 V.
AC ELECTRICAL CHARACTERISTICS FOR ACT
TA = +25°C, CL = 50 pF
Symbol
Parameter
TA = −40°C to +85°C, CL = 50 pF
VCC(V) (Note 7)
Min
Typ
Max
Min
Max
Unit
tPLH
Propagation Delay
5.0
1.0
6.0
8.5
1.0
9.0
ns
tPLH
Propagation Delay
5.0
1.0
5.5
8.0
1.0
8.5
ns
7. Voltage range 5.0 is 5.0 V + 0.5 V.
CAPACITANCE
Symbol
Parameter
Conditions
Typ
Unit
CIN
Input Capacitance
VCC = OPEN
4.5
pF
VCC
Power Dissipation Capacitance
VCC = 5.0 V
30.0
pF
FACT is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or
other countries.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC14
CASE 751EF
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13739G
SOIC14
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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