74ACT109MTC

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description ■ ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs Asynchronous Inputs: – – – – LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number Package Number Package Description 74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC109MTC MTC16 74ACT109SC M16A 74AC109MTC MTC16 74ACT109PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names Description J1, J2, K1, K2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q2, Q1, Q2 Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop March 2007 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Logic Symbols IEEE/IEC Truth Table Each half. Inputs Outputs SD CD CP J K Q Q L H X X X H L H L X X X L H X L L X X H H H H L L L H H H H L H H L H H H H H H L H H X X Q0 Q0 L Toggle Q0 Q0 H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock Logic Diagram One half shown. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Diode Current VI = –0.5V –20mA VI = VCC + 0.5V +20mA VI DC Input Voltage IOK DC Output Diode Current –0.5V to VCC + 0.5V VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.5V IO DC Output Source or Sink Current ±50mA ICC or IGND DC VCC or Ground Current per Output Pin ±50mA TSTG Storage Temperature –65°C to +150°C TJ Junction Temperature 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI Parameter Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage VO Output Voltage TA Operating Temperature ∆V / ∆t Rating 0V to VCC 0V to VCC –40°C to +85°C Minimum Input Edge Rate, AC Devices: 125mV/ns VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V ∆V / ∆t Minimum Input Edge Rate, ACT Devices: 125mV/ns VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 3 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V Maximum LOW Level Input Voltage 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 4.5 3.0 4.5 VOUT = 0.1V or VCC – 0.1V 5.5 VOH Minimum HIGH Level Output Voltage Guaranteed Limits 1.5 5.5 VIL Typ. TA = –40°C to +85°C 3.0 IOUT = –50µA Units V V V VIN = VIL or VIH: VOL Maximum LOW Level Output Voltage 3.0 IOH = –12mA 2.56 2.46 4.5 IOH = –24mA 3.86 3.76 4.86 4.76 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 0.36 0.44 –24mA(1) 5.5 IOH = 3.0 IOUT = 50µA V VIN = VIL or VIH: 3.0 IOL = 12mA 4.5 IOL = 24mA 0.36 0.44 5.5 IOL = 24mA(1) 0.36 0.44 VI = VCC, GND ±0.1 ±1.0 µA VOLD = 1.65V Max. 75 mA VOHD = 3.85V Min. –75 mA 20.0 µA IIN(3) Maximum Input Leakage Current 5.5 IOLD Minimum Dynamic Output Current(2) 5.5 Maximum Quiescent Supply Current 5.5 IOHD ICC (3) VIN = VCC or GND 2.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 4 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter VCC (V) 1.5 2.0 2.0 VOUT = 0.1V or VCC – 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = –50µA 4.49 4.4 4.4 5.49 5.4 5.4 3.86 3.76 4.86 4.76 0.001 0.1 0.1 0.001 0.1 0.1 0.36 0.44 0.36 0.44 ±0.1 ± 1.0 µA 1.5 mA 75 mA –75 mA 20.0 µA Maximum LOW Level Input Voltage 4.5 Minimum HIGH Level Output Voltage 5.5 5.5 V V V VIN = VIL or VIH: IOH = –24mA –24mA(4) 5.5 IOH = 4.5 IOUT = 50µA 5.5 V VIN = VIL or VIH: IOL = 24mA 24mA(4) IOL = Maximum Input Leakage Current 5.5 VI = VCC, GND ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V IOLD Minimum Dynamic Output Current(5) 5.5 VOLD = 1.65V Max. Maximum Quiescent Supply Current 5.5 ICC Units 2.0 5.5 IOHD Guaranteed Limits 2.0 4.5 IIN Typ. 1.5 4.5 Maximum LOW Level Output Voltage Conditions TA = –40°C to +85°C VOUT = 0.1V or VCC – 0.1V Minimum HIGH Level Input Voltage 4.5 VOL TA = +25°C 0.6 VOHD = 3.85V Min. VIN = VCC or GND 2.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 5 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop DC Electrical Characteristics for ACT TA = +25°C, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL TA = –40°C to +85°C, CL = 50pF VCC (V)(6) Min. Typ. 3.3 125 150 100 5.0 150 175 125 Propagation Delay, CPn to Qn or Qn 3.3 4.0 8.0 13.5 3.5 16.0 5.0 2.5 6.0 10.0 2.0 10.5 Propagation Delay, CPn to Qn or Qn 3.3 3.0 8.0 14.0 3.0 14.5 5.0 2.0 6.0 10.0 1.5 10.5 Propagation Delay, CDn or SDn to Qn or Qn 3.3 3.0 8.0 12.0 2.5 13.0 5.0 2.5 6.0 9.0 2.0 10.0 Propagation Delay, CDn or SDn to Qn or Qn 3.3 3.0 10.0 12.0 3.0 13.5 5.0 2.0 7.5 9.5 2.0 10.5 Parameter Maximum Clock Frequency Max. Min. Max. Units MHz ns ns ns ns Note: 6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. AC Operating Requirements for AC TA = +25°C, CL = 50pF Symbol tS tH tW tREC TA = –40°C to +85°C, CL = 50 pF VCC (V)(7) Typ. Setup Time, HIGH or LOW, Jn or Kn to CPn 3.3 3.5 6.5 7.5 5.0 2.0 4.5 5.0 Hold Time, HIGH or LOW, Jn or Kn to CPn 3.3 –1.5 0 0 5.0 –0.5 0.5 0.5 Pulse Width, CDn or SDn 3.3 2.0 7.0 7.5 5.0 2.0 4.5 5.0 3.3 –2.5 0 0 5.0 –1.5 0 0 Parameter Recovery Time, CDn or SDn to CPn Guaranteed Minimum Units ns ns ns ns Note: 7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 6 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop AC Electrical Characteristics for AC TA = +25°C, CL = 50pF Symbol Parameter TA = –40°C to +85°C, CL = 50pF VCC (V)(8) Min. Typ. Max. Min. 125 Max. Units fMAX Maximum Clock Frequency 5.0 145 210 MHz tPLH Propagation Delay, CPn to Qn or Qn 5.0 4.0 7.0 11.0 3.5 13.0 ns tPHL Propagation Delay, CPn to Qn or Qn 5.0 3.0 6.0 10.0 2.5 11.5 ns tPLH Propagation Delay, CDn or SDn to Qn or Qn 5.0 2.5 5.5 9.5 2.0 10.5 ns tPHL Propagation Delay 5.0 2.5 6.0 10.0 2.0 11.5 ns CDn or SDn to Qn or Qn Note: 8. Voltage range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT TA = +25°C, CL = 50pF Symbol Parameter VCC (V)(9) Typ. TA = –40°C to +85°C, CL = 50pF Guaranteed Minimum Units tS Setup Time, HIGH or LOW, Jn or Kn to CPn 5.0 0.5 2.0 2.5 ns tH Hold Time, HIGH or LOW, Jn or Kn to CPn 5.0 0 2.0 2.0 ns tW Pulse Width, CPn or CDn or SDn 5.0 3.0 5.0 6.0 ns trec Recovery Time, CDn or SDn to CPn 5.0 –2.5 0 0 ns Note: 9. Voltage range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = OPEN 4.5 pF CPD Power Dissipation Capacitance VCC = 5.0V 35.0 pF ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 7 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop AC Electrical Characteristics for ACT 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 8 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 9 5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 10 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 11 ® ACEx Across the board. Around the world.¥ ActiveArray¥ Bottomless¥ Build it Now¥ CoolFET¥ CROSSVOLT¥ CTL™ Current Transfer Logic™ DOME¥ 2 E CMOS¥ ® EcoSPARK EnSigna¥ FACT Quiet Series™ ® FACT ® FAST FASTr¥ FPS¥ ® FRFET GlobalOptoisolator¥ GTO¥ HiSeC¥ i-Lo¥ ImpliedDisconnect¥ IntelliMAX¥ ISOPLANAR¥ MICROCOUPLER¥ MicroPak¥ MICROWIRE¥ MSX¥ MSXPro¥ OCX¥ OCXPro¥ ® OPTOLOGIC ® OPTOPLANAR PACMAN¥ POP¥ ® Power220 ® Power247 PowerEdge¥ PowerSaver¥ ® PowerTrench Programmable Active Droop¥ ® QFET QS¥ QT Optoelectronics¥ Quiet Series¥ RapidConfigure¥ RapidConnect¥ ScalarPump¥ SMART START¥ ® SPM STEALTH™ SuperFET¥ SuperSOT¥-3 SuperSOT¥-6 SuperSOT¥-8 SyncFET™ TCM¥ ® The Power Franchise ® TinyLogic TINYOPTO¥ TinyPower¥ TinyWire¥ TruTranslation¥ PSerDes¥ ® UHC UniFET¥ VCX¥ Wire¥ ™ TinyBoost¥ TinyBuck¥ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 ©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 12 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.