74ACT163SJX

Revised February 2000 74AC163 • 74ACT163 Synchronous Presettable Binary Counter General Description Features The AC/ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. ■ ICC reduced by 50% ■ Synchronous counting and loading ■ High-speed synchronous expansion ■ Typical count rate of 125 MHz ■ Outputs source/sink 24 mA ■ ACT163 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide 74AC163SJ 74AC163MTC 74AC163PC MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74ACT163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT163MTC 74ACT163PC MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 2000 Fairchild Semiconductor Corporation DS009932 Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input SR Synchronous Reset Input P0–P3 Parallel Data Inputs PE Parallel Enable Input Q0–Q3 Flip-Flop Outputs TC Terminal Count Output www.fairchildsemi.com 74AC163 • 74ACT163 Synchronous Presettable Binary Counter November 1988 74AC163 • 74ACT163 Logic Symbols Functional Description The AC/ACT163 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputs—Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and SR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. IEEE/IEC The AC/ACT163 uses D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Mode Select Table SR PE CET CEP L X X X Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Action on the Rising Clock Edge (  ) Reset (Clear) H L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET www.fairchildsemi.com 2 74AC163 • 74ACT163 State Diagram FIGURE 1. FIGURE 2. Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74AC163 • 74ACT163 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V AC Devices VIN from 30% to 70% of VCC ±50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Source or Sink Current (IO) AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 0.1 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V V or VCC − 0.1V V IOUT = −50 µA VOUT = 0.1V VIN = VIL or VIH VOL 0.002 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µA VI = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 5.5 40.0 µA VIN = VCC (Note 4) Supply Current V IOUT = 50 µA VIN = VILor VIH 4.0 V IOL = 24 mA IOL = 24 mA (Note 2) or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com IOL = 12 mA 4 74AC163 • 74ACT163 DC Electrical Characteristics for ACT Symbol Parameter VIL VOH TA = −40°C to +85°C (V) Typ 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Minimum HIGH Level VIH TA = +25°C VCC Guaranteed Limits Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 IOH = −24 mA (Note 5) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH 5.5 0.36 0.44 IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA VI = VCC, GND ICCT Maximum 5.5 1.5 mA VI = VCC − 2.1V 0.6 IOL = 24 mA (Note 5) ICC/Input IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 5.5 40.0 µA VIN = VCC 4.0 Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL Parameter VCC TA = +25°C TA = −40°C to +85°C (V) CL = 50 pF CL = 50 pF (Note 7) Min Typ Maximum Clock 3.3 70 95 Max Min 60 Frequency 5.0 110 140 95 Propagation Delay, CP to Qn 3.3 2.0 7.5 12.5 1.5 13.5 (PE Input HIGH or LOW) 5.0 1.5 5.5 9.0 1.0 9.5 Propagation Delay, CP to Qn 3.3 1.5 8.5 12.0 1.5 13.0 (PE Input HIGH or LOW) 5.0 1.5 6.0 9.5 1.5 10.0 Propagation Delay 3.3 3.0 9.5 15.0 2.5 16.5 CP to TC 5.0 2.0 7.0 10.5 1.5 11.5 Propagation Delay 3.3 3.5 11.0 14.0 2.5 15.5 CP to TC 5.0 2.0 8.0 11.0 2.0 11.5 Propagation Delay 3.3 2.0 7.5 9.5 1.5 11.0 CET to TC 5.0 1.5 5.5 6.5 1.0 7.5 Propagation Delay 3.3 2.5 8.5 11.0 2.0 12.5 CET to TC 5.0 2.0 6.0 8.5 1.5 9.5 Units Max MHz ns ns ns ns ns ns Note 7: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V 5 www.fairchildsemi.com 74AC163 • 74ACT163 AC Operating Requirements for AC Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 8) tS TA = −40°C to +85°C CL = 50 pF Typ Units Guaranteed Minimum Setup Time, HIGH or LOW 3.3 5.5 13.5 16.0 Pn to CP 5.0 4.0 8.5 10.5 ns tH tS Hold Time, HIGH or LOW 3.3 −7.0 −1.0 −0.5 Pn to CP 5.0 −5.0 0 0 Setup Time, HIGH or LOW 3.3 5.5 14.0 16.5 SR to CP 5.0 4.0 9.5 11.0 ns ns tH tS Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 SR to CP 5.0 −5.5 −0.5 0 Setup Time, HIGH or LOW 3.3 5.5 11.5 14.0 PE to CP 5.0 4.0 7.5 8.5 ns ns tH tS Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 PE to CP 5.0 −5.0 −0.5 0 Setup Time, HIGH or LOW 3.3 3.5 6.0 7.0 CEP or CET to CP 5.0 2.5 4.5 5.0 Hold Time, HIGH or LOW 3.3 −4.5 0 0 CEP or CET to CP 5.0 −3.0 0 0.5 ns ns tH tW ns Clock Pulse Width (Load) 3.3 3.0 3.5 4.0 HIGH or LOW 5.0 2.0 2.5 3.0 ns tW Clock Pulse Width (Count) 3.3 3.0 4.0 4.5 HIGH or LOW 5.0 2.0 3.0 3.5 ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay, CP to Qn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 9) Min Typ Max 5.0 120 140 5.0 1.5 5.5 10.0 1.5 11.0 ns 5.0 1.5 6.0 11.0 1.5 12.0 ns 5.0 2.5 7.0 11.5 2.0 13.5 ns 5.0 3.0 8.0 13.5 2.0 15.0 ns 5.0 2.0 5.5 9.0 1.5 10.5 ns 5.0 2.0 6.0 10.0 2.0 11.0 ns 105 MHz (PE Input HIGH or LOW) tPHL Propagation Delay, CP to Qn (PE Input HIGH or LOW) tPLH Propagation Delay CP to TC tPHL Propagation Delay CP to TC tPLH Propagation Delay CET to TC tPHL Propagation Delay CET to TC Note 9: Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 6 Symbol tS Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 10) Typ Guaranteed Minimum 5.0 4.0 10.0 12.0 ns 5.0 −5.0 0.5 0.5 ns 5.0 4.0 10.0 11.5 ns 5.0 −5.5 −0.5 −0.5 ns 5.0 4.0 8.5 10.5 ns 5.0 −5.5 −0.5 0 ns 5.0 2.5 5.5 6.5 ns 5.0 −3.0 0 0.5 ns 5.0 2.0 3.5 3.5 ns 5.0 2.0 3.5 3.5 ns Setup Time, HIGH or LOW Pn to CP tH Hold Time, HIGH or LOW Pn to CP tS Setup Time, HIGH or LOW SR to CP tH Hold Time, HIGH or LOW SR to CP tS Setup Time, HIGH or LOW PE to CP tH Hold Time, HIGH or LOW PE to CP tS Setup Time, HIGH or LOW CEP or CET to CP tH Hold Time, HIGH or LOW CEP or CET to CP tW Clock Pulse Width (Load) HIGH or LOW tW Clock Pulse Width (Count) HIGH or LOW Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 45.0 pF VCC = 5.0V 7 Conditions www.fairchildsemi.com 74AC163 • 74ACT163 AC Operating Requirements for ACT 74AC163 • 74ACT163 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A www.fairchildsemi.com 8 74AC163 • 74ACT163 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 9 www.fairchildsemi.com 74AC163 • 74ACT163 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 10 74AC163 • 74ACT163 Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com