74ACT18823MTD

Revised October 1999 74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACT18823 contains eighteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP), Clear (CLR), Clock Enable (EN) and Output Enable (OE) are common to each byte and can be shorted together for full 18-bit operation. ■ Broadside pinout allows for easy board layout ■ Separate control logic for each byte ■ Extra data width for wider address/data paths or buses carrying parity ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT18823SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACT18823MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) CLRn Clear (Active LOW) ENn Clock Enable (Active LOW) CPn Clock Pulse Input I0–I17 Inputs O0–O17 Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS500294 www.fairchildsemi.com 74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs August 1999 74ACT18823 Functional Description Function Table The ACT18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock (CPn) and buffered Output Enable (OEn) are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLRn) and Clock Enable (ENn) pins. These devices are ideal for parity bus interfacing in high performance systems. (Note 1) Inputs OE CLR When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions. H X L H X L CP   In Q On Function L L Z High Z H H Z High Z H L X X X L Z Clear L L X X X L L Clear H H H X X NC Z Hold L H H X X NC NC Hold H H L H H L L H L L H L     L L Z Load H H Z Load L L L Load H H H Load H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial Z= High Impedance = LOW-to-HIGH Transition NC= No Change  Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically. Logic Diagrams Byte 1 (0:8) Byte 2 (9:17) www.fairchildsemi.com EN Internal Output 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V ± 50 mA Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC VCC or Ground Current ± 50 mA Per Output Pin 0V to VCC Output Voltage (VO) Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) 4.5V to 5.5V Input Voltage (VI) Junction Temperature +140°C PDIP/SOIC −65°C to +150°C Storage Temperature DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH VCC TA = +25°C (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 Units V V V Conditions VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 V IOH = −24 mA IOH = −24 mA (Note 3) Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.5 ±5.0 µA ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC −2.1V 80.0 µA VIN = VCC or GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IOZ Maximum 3-STATE Leakage Current IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 ICC Maximum Quiescent Supply Current 5.5 IOLD Minimum Dynamic IOHD Output Current (Note 4) 0.6 8.0 5.5 IOL = 24 mA (Note 3) VI = VIL, VIH VO = VCC, GND Note 3: All outputs loaded; thresholds associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT18823 Absolute Maximum Ratings(Note 2) 74ACT18823 AC Electrical Characteristics Symbol fMAX Parameter VCC TA = +25°C (V) CL = 50 pF (Note 5) Min 5.0 100 TA = −40°C to +85°C CL = 50 pF Max Min Units Max Maximum Clock 90 MHz Frequency tPHL Propagation Delay tPLH CPn to On tPHL Propagation Delay 2.0 9.0 2.0 9.5 2.0 9.0 2.0 9.5 2.0 9.0 2.0 9.5 5.0 ns 5.0 ns CLRn to On tPZL Output Enable Time 2.0 9.0 2.0 10.0 2.0 9.0 2.0 10.0 5.0 ns tPZH tPLZ Output Disable Time 1.5 7.0 1.5 7.5 1.5 8.0 1.5 8.5 5.0 ns tPHZ Note 5: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements Symbol Parameter VCC TA = +25°C TA = −40°C to +85°C (V) CL = 50 pF CL = 50 pF (Note 6) tS Units Guaranteed Minimum Setup Time, HIGH or LOW, 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns 5.0 4.0 4.0 ns 5.0 6.0 6.0 ns Input to Clock tH Hold Time, HIGH or LOW, Input to Clock tS Setup Time, HIGH or LOW, Enable to Clock tH Hold Time, HIGH or LOW, Enable to Clock tW CPn Pulse Width, HIGH or LOW tW CLRn Pulse Width, HIGH or LOW trec Recovery Time, CLRn to CPn Note 6: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 95 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions 74ACT18823 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A 5 www.fairchildsemi.com 74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6