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74ACT18825MTDX

74ACT18825MTDX

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    TSSOP56_14X6.1MM

  • 描述:

    IC BUF NON-INVERT 5.5V 56TSSOP

  • 数据手册
  • 价格&库存
74ACT18825MTDX 数据手册
Revised October 1999 74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs General Description Features The ACT18825 contains eighteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 18-bit operation. ■ Broadside pinout allows for easy board layout ■ Separate control logic for each byte ■ Extra data width for wider address/data paths or buses carrying parity ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT18825SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACT18825MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) I0–I17 Inputs O0–O17 Outputs FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS0500292 www.fairchildsemi.com 74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs August 1999 74ACT18825 Functional Description Truth Table The ACT18825 contains eighteen non-inverting buffers with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independently of the other. The control pins may be shorted together to obtain full 8-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Inputs OE1 OE2 OE3 OE4 Logic Diagram 2 I0–I8 I9–I17 O0–O8 O9–O17 L L L L H H H H H X L L X L Z L X H L L X H Z H L L H X L X L Z L L X H H X H Z H H H H X X Z Z L L L L L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance www.fairchildsemi.com Outputs Byte 1 (0:8) Byte 2 (8:17) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO) 0V to VCC Output Voltage (VO) 0V to VCC VCC @ 4.5V, 5.5V ±50 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ±50 mA Per Output Pin 125 mV/ns VIN from 0.8V to 2.0V DC VCC or Ground Current Storage Temperature −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V∆t) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) 4.5V to 5.5V Input Voltage (VI) −65°C to +150°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC TA = +25°C (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 Units V V V Conditions VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IOZ Maximum 3-STATE Leakage Current 0.36 0.44 0.36 0.44 5.5 ±0.5 ±5.0 µA 5.5 ± 0.1 ± 1.0 µA 1.5 mA VI = VCC −2.1V 8.0 80.0 µA VIN = VCC or GND IIN Maximum Input Leakage Current ICCT Maximum ICC/Input 5.5 ICC Maximum Quiescent Supply Current 5.5 IOLD Minimum Dynamic IOHD Output Current (Note 3) 0.6 5.5 V IOL = 24 mA 4.5 5.5 IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT18825 Absolute Maximum Ratings(Note 1) 74ACT18825 AC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 4) tPHL Propagation Delay tPLH Data to Output tPZL Output Enable tPZH Time tPLZ Output Disable tPHZ Time 5.0 5.0 5.0 TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max 2.0 5.3 8.4 2.0 9.0 2.0 5.6 8.7 2.0 9.2 2.0 6.3 9.6 2.0 10.3 2.0 6.5 9.7 2.0 10.4 1.5 4.5 7.3 1.5 7.6 1.5 5.1 8.5 1.5 8.8 Note 4: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter Typ Units Conditions CIN Input Pin Capacitance 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 95 pF VCC = 5.0V www.fairchildsemi.com 4 Units ns ns ns 74ACT18825 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A 5 www.fairchildsemi.com 74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6
74ACT18825MTDX 价格&库存

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