Revised November 1999
74AC299 • 74ACT299
8-Input Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
Features
The AC/ACT299 is an 8-bit universal shift/storage register
with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial
cascading. A separate active LOW Master Reset is used to
reset the register.
■ ICC and IOZ reduced by 50%
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load
and store
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ ACT299 has TTL-compatible inputs
Ordering Code:
Order Number
Package Number
74AC299SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC299SJ
74AC299MTC
MTC20
Package Description
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC299PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT299SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT299MTC
74ACT299PC
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
CP
Clock Pulse Input
DS0
Serial Data Input for Right Shift
DS7
Serial Data Input for Left Shift
S0, S1
Mode Select Inputs
MR
Asynchronous Master Reset
OE1, OE2
3-STATE Output Enable Inputs
I/O0–I/O7
Parallel Data Inputs or
Q0, Q7
Serial Outputs
3-STATE Parallel Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009893
www.fairchildsemi.com
74AC299 • 74ACT299 8-Input Universal Shift/Storage Register
July 1988
74AC299 • 74ACT299
Logic Symbols
Truth Table
Inputs
MR S1
IEEE/IEC
Response
S0
CP
L
X
X
H
H
H
H
L
H
H
H
L
H
L
L
X
X
Asynchronous Reset; Q0–Q7 = LOW
Parallel Load; I/On → Qn
Shift Right; DS0 → Q0, Q0 → Q1, etc.
Shift Left, DS7 → Q7, Q7 → Q6, etc.
Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as
shown in the Truth Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S0 and S1 in preparation for a parallel load operation.
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74AC299 • 74ACT299
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74AC299 • 74ACT299
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC +0.5V
+20 mA
Supply Voltage (VCC)
(Unless Otherwise Specified)
−0.5V to VCC +0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
−20 mA
VO = VCC +0.5V
+20 mA
DC Output Voltage (VO)
Storage Temperature (TSTG)
4.5V to 5.0V
0V to VCC
Output Voltage (VO)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
± 50 mA
AC Devices
± 50 mA
VCC @ 3.3V, 4.5V, 5.5V
DC VCC or Ground Current
Per Output Pin (ICC or IGND)
2.0V to 6.0V
ACT
Input Voltage (VI)
−0.5V to VCC +0.5V
DC Output Source or Sink Current (IO)
AC
VIN from 30% to 70% of VCC
−65°C to +150°C
125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
Junction Temperature (TJ)
ACT Devices
(PDIP)
140°C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
Parameter
VCC
TA = 25°C
TA = −40°C to +85°C
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
3.0
1.5
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
2.1
Units
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Conditions
VOUT = 0.1V
2.1
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH = −12 mA
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
IOH = −24 mA
5.5
4.86
4.76
IOH = −24 mA (Note 2)
0.1
0.1
VIN = VIL or VIH
VOL
Maximum LOW Level
Output Voltage
3.0
0.002
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
± 0.1
± 1.0
V
IOUT = 50 µA
VIN = VIL or VIH
IIN
Maximum Input
(Note 4)
Leakage Current
IOLD
Minimum Dynamic
IOHD
Output Current (Note 3)
ICC (Note 4)
Maximum Quiescent
Supply Current
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5.5
5.5
4.0
4
IOH = 12 mA
V
IOH = 24 mA
IOH = 24 mA (Note 2)
µA
VI = VCC, GND
86
mA
VOLD = 1.65V Max
−75
mA
VOHD = 3.85V Min
40.0
µA
VIN = VCC or GND
Symbol
Parameter
VCC
(V)
IOZT
(Continued)
TA = 25°C
Typ
TA = −40°C to +85°C
Units
Conditions
Guaranteed Limits
VI (OE) = VIL, VIH
Maximum I/O Leakage Current
± 0.3
5.5
± 3.0
µA
VI = VCC, GND
VO = VCC, GND
Note 2: All outputs loaded; threshold on input associated with output under test.
Note 3: Maximum test duration 20 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
Parameter
VCC
TA = 25°C
(V)
Typ
TA = −40°C to +85°C
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
3.0
1.5
0.8
0.8
Input Voltage
4.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
4.5
0.0001
3.86
3.76
Units
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH = −24 mA
VIN = VIL or VIH
5.5
VOL
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
0.36
0.44
IOH = −24 mA (Note 5)
V
IOUT = 50 µA
V
IOL= 24 mA
VIN = VIL or VIH
4.5
IOL= 24 mA (Note 5)
5.5
0.36
0.44
IIN
Maximum Input Leakage Current
5.5
± 0.1
± 1.0
µA
VI = VCC, GND
ICCT
Maximum ICC/Input
5.5
1.5
mA
VI = VCC − 2.1V
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 6)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent Supply Current
5.5
40.0
µA
IOZT
Maximum I/O
Leakage Current
0.6
4.0
VIN = VCC or GND
VI (OE) = VIL, VIH
±0.3
5.5
±3.0
µA
VI = VCC, GND
VO = VCC, GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
5
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74AC299 • 74ACT299
DC Electrical Characteristics for AC
74AC299 • 74ACT299
AC Electrical Characteristics for AC
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
(Note 7)
fMAX
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
Min
Typ
TA = −40°C to +85°C
CL = 50 pF
Max
Min
Maximum Input
3.3
90
124
80
Frequency
5.0
130
173
105
Units
Max
MHz
Propagation Delay
3.3
8.5
14.0
20.5
7.0
22.0
CP to Q0 or Q7 (Shift Left or Right)
5.0
5.5
9.5
14.0
4.5
15.0
Propagation Delay
3.3
8.5
14.5
21.5
7.0
23.0
CP to Q0 or Q7 (Shift Left or Right)
5.0
5.5
10.0
14.5
5.0
16.0
Propagation Delay
3.3
9.0
14.5
20.5
7.5
22.5
CP to I/On
5.0
6.0
10.0
14.5
5.0
16.0
Propagation Delay
3.3
10.0
16.0
23.0
8.5
24.5
CP to I/On
5.0
6.5
11.0
16.0
6.0
17.5
Propagation Delay
3.3
9.0
15.5
22.5
7.5
25.0
MR to Q0 or Q7
5.0
5.5
10.5
15.5
5.0
17.0
Propagation Delay
3.3
9.0
15.0
21.5
7.5
24.0
MR to I/On
5.0
5.5
10.0
15.0
5.0
16.5
Output Enable Time
3.3
7.0
12.0
18.0
6.0
19.5
OE to I/On
5.0
4.5
8.5
12.5
4.0
13.5
Output Enable Time
3.3
7.0
12.5
18.0
6.0
20.5
OE to I/On
5.0
5.0
8.0
12.5
4.0
14.0
Output Disable Time
3.3
6.5
13.0
18.5
5.5
19.5
OE to I/On
5.0
3.5
9.5
14.0
3.0
15.0
Output Disable Time
3.3
5.5
11.5
17.0
4.5
19.0
OE to I/On
5.0
3.5
8.0
12.5
2.0
13.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V.
Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for AC
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
(Note 8)
tS
tH
tS
tH
tS
tH
tW
tW
tREC
TA = −40°C to +85°C
CL = 50 pF
Typ
Setup Time, HIGH or LOW
3.3
3.0
8.0
8.5
S0 or S1 to CP
5.0
2.0
5.0
5.5
Hold Time, HIGH or LOW
3.3
−3.0
0.5
0.5
S0 or S1 to CP
5.0
−1.5
1.0
1.0
Setup Time, HIGH or LOW
3.3
2.0
5.5
6.0
I/On to CP
5.0
1.0
3.5
4.0
Hold Time, HIGH or LOW
3.3
−2.0
0
0
I/On to CP
5.0
−1.0
1.0
1.0
Setup Time, HIGH or LOW
3.3
2.5
6.5
7.0
DS0 or DS7 to CP
5.0
1.5
4.0
4.5
Hold Time, HIGH or LOW
3.3
−2.0
0
0.5
DS0 or DS7 to CP
5.0
−1.0
1.0
1.0
CP Pulse Width, LOW
3.3
3.5
4.5
5.0
5.0
2.0
3.5
3.5
3.3
4.0
4.5
5.0
5.0
2.0
3.5
3.5
MR Pulse Width, LOW
Recovery Time
3.3
0
1.5
1.5
MR to CP
5.0
0.5
1.5
1.5
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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6
Units
Guaranteed Minimum
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
fMAX
Maximum Input Frequency
tPLH
Propagation Delay
CP to Q0 or Q7 (Shift Left or Right)
tPHL
Propagation Delay
CP to Q0 or Q7 (Shift Left or Right)
tPLH
Propagation Delay
CP to I/On
tPHL
Propagation Delay
CP to I/On
tPHL
Propagation Delay
MR to Q0 or Q7
tPHL
Propagation Delay
MR to I/On
tPZH
Output Enable Time
OE to I/On
tPZL
Output Enable Time
OE to I/On
tPHZ
Output Disable Time
OE to I/On
tPLZ
Output Disable Time
OE to I/On
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Max
Min
Units
(Note 9)
Min
Typ
Max
5.0
120
170
5.0
4.0
8.5
12.5
3.0
14.0
ns
5.0
4.0
9.0
13.5
3.5
15.0
ns
5.0
4.5
8.5
12.5
4.5
13.5
ns
5.0
5.0
9.5
15.0
4.5
16.5
ns
5.0
4.0
14.0
15.0
4.0
18.0
ns
5.0
4.0
13.0
14.5
3.5
17.5
ns
5.0
2.5
8.0
12.0
1.5
13.0
ns
5.0
2.0
8.0
12.0
1.5
13.5
ns
5.0
2.0
8.5
12.5
2.0
13.5
ns
5.0
2.5
8.0
11.5
2.0
12.5
ns
110
MHz
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
Symbol
tS
Parameter
Setup Time, HIGH or LOW
S0 or S1 to CP
Hold Time, HIGH or LOW
tH
S0 or S1 to CP
tS
Setup Time, HIGH or LOW
I/On to CP
tH
Hold Time, HIGH or LOW
I/On to CP
tS
Setup Time, HIGH or LOW
DS0 or DS7 to CP
Hold Time, HIGH or LOW
tH
DS0 or DS7 to CP
tW
CP Pulse Width
HIGH or LOW
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 10)
Typ
Guaranteed Minimum
5.0
2.0
5.0
5.5
ns
5.0
−2.0
1.0
1.0
ns
5.0
1.5
4.0
4.5
ns
5.0
−1.0
1.0
1.0
ns
5.0
1.5
4.5
5.0
ns
5.0
−1.0
1.0
1.0
ns
5.0
2.0
4.0
4.5
ns
tW
MR Pulse Width, LOW
5.0
2.0
3.5
3.5
ns
tREC
Recovery Time, MR to CP
5.0
0
1.5
1.5
ns
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
170
pF
VCC = 5.5V
7
Conditions
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74AC299 • 74ACT299
AC Electrical Characteristics for ACT
74AC299 • 74ACT299
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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8
74AC299 • 74ACT299
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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74AC299 • 74ACT299
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
74AC299 • 74ACT299 8-Input Universal Shift/Storage Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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