74ACT373MSA

Revised November 1999 74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs General Description Features The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. ■ ICC and IOZ reduced by 50% ■ Eight latches in a single package ■ 3-STATE outputs for bus interfacing ■ Outputs source/sink 24 mA ■ ACT373 has TTL-compatible inputs Ordering Code: Order Number Package Number 74AC373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC373SJ 74AC373MTC MTC20 74AC373PC Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ACT373SJ M20D 74ACT373MSA MSA20 74ACT373MTC MTC20 74ACT373PC N20A 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009958 www.fairchildsemi.com 74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs November 1988 74AC373 • 74ACT373 Functional Description Truth Table The AC/ACT373 contains eight D-type latches with 3STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE OE Dn On Z X H X H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL IOH = −12 mA V IOH = −24 mA IOL = −24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA 5.5 ±0.25 ± 2.5 µA VI = VCC, GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min 40.0 µA VIN = VCC or GND V IOUT = 50 µA VIN = VIL or VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE Current IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = VIL, VIH VO = VCC, GND IOLD Minimum Dynamic Output Current (Note 3) 5.5 Maximum Quiescent Supply Current 5.5 IOHD ICC (Note 4) 5.5 4.0 Note 2: All outputs loaded, thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC373 • 74ACT373 Absolute Maximum Ratings(Note 1) 74AC373 • 74ACT373 DC Electrical Characteristics for ACT Symbol Parameter VIL VOH TA = −40°C to +85° (V) Typ 4.5 1.5 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Minimum HIGH Level VIH TA = +25°C VCC Guaranteed Limits 2.0 2.0 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH= −24 mA (Note 5) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA 5.5 ± 0.25 ± 2.5 µA 1.5 mA V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current 0.6 VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V ICCT Maximum ICC/Input IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA Supply Current 5.5 IOL = 24 mA (Note 5) 5.5 4.0 VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Max Min Max Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0 Dn to On 5.0 1.5 7.0 9.5 1.5 10.5 Propagation Delay 3.3 1.5 9.5 13.0 1.5 14.5 Dn to On 5.0 1.5 7.0 9.5 1.5 10.5 Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0 LE to On 5.0 1.5 7.5 9.5 1.5 10.5 Propagation Delay 3.3 1.5 9.5 12.5 1.5 14.0 LE to On 5.0 1.5 7.0 9.5 1.5 10.5 Output Enable Time 3.3 1.5 9.0 11.5 1.0 13.0 5.0 1.5 7.0 8.5 1.0 9.5 3.3 1.5 8.5 11.5 1.0 13.0 5.0 1.5 6.5 8.5 1.0 9.5 Output Enable Time Output Disable Time Output Disable Time 3.3 1.5 10.0 12.5 1.0 14.5 5.0 1.5 8.0 11.0 1.0 12.5 3.3 1.5 8.0 11.5 1.0 12.5 5.0 1.5 6.5 8.5 1.0 10.0 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Units ns ns ns ns ns ns ns ns Symbol tS tH tW Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 8) Typ Setup Time, HIGH or LOW 3.3 3.5 5.5 6.0 Dn to LE 5.0 2.0 4.0 4.5 Units Guaranteed Minimum Hold Time, HIGH or LOW 3.3 −3.0 1.0 1.0 Dn to LE 5.0 −1.5 1.0 1.0 LE Pulse Width, 3.3 4.0 5.5 6.0 HIGH 5.0 2.0 4.0 4.5 ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol tPLH Parameter Propagation Delay Dn to On tPHL Propagation Delay Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 9) Min Typ Max Min Max 5.0 2.5 8.5 10.0 1.5 11.5 ns 5.0 2.0 8.0 10.0 1.5 11.5 ns 5.0 2.5 8.5 11.0 2.0 11.5 ns 5.0 2.0 8.0 10.0 1.5 11.5 ns ns tPZH Output Enable Time 5.0 2.0 8.0 9.5 1.5 10.5 tPZL Output Enable Time 5.0 2.0 7.5 9.0 1.5 10.5 ns tPHZ Output Disable Time 5.0 2.5 9.0 11.0 2.5 12.5 ns tPLZ Output Disable Time 5.0 1.5 7.5 8.5 1.0 10.0 ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Symbol Parameter Setup Time, HIGH or LOW tS Dn to LE tH Hold Time, HIGH or LOW Dn to LE tW LE Pulse Width, HIGH VCC TA = +25°C (V) CL = 50 pF (Note 10) Typ 5.0 0.8 TA = −40°C to +85°C CL = 50 pF Units Guaranteed Minimum 2.5 3.5 ns 5.0 0 0 1.0 ns 5.0 2.0 7.0 8.0 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 40.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC373 • 74ACT373 AC Operating Requirements for AC 74AC373 • 74ACT373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 6 74AC373 • 74ACT373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74AC373 • 74ACT373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74AC373 • 74ACT373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 9 www.fairchildsemi.com 74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10