74ACT534SC

Revised November 1999 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACT534 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. The ACT534 is the same as the ACT374 except that the outputs are inverted. ■ ICC and IOZ reduced by 50% ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ 3-STATE outputs for bus-oriented applications ■ Outputs source/sink 24 mA ■ ACT534 has TTL-compatible inputs ■ Inverted output version of ACT374 Ordering Code: Order Number Package Number 74ACT534SC M20B Package Description 74ACT534SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT534PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 Complementary 3-STATE Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009965 www.fairchildsemi.com 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs November 1988 74ACT534 Functional Description transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ACT534 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) Function Table Inputs CP Output   OE D L H O L L L H L L X O0 X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Z = High Impedance O0 = Value stored from previous clock cycle  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units Conditions Guaranteed Limits V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 2) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA 1.5 mA VI = VCC − 2.1V V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current ICCT Maximum ICC/Input 5.5 0.6 IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA Supply Current 5.5 4.0 VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT534 Absolute Maximum Ratings(Note 1) 74ACT534 AC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 4) fMAX Maximum Clock Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn CL = 50 pF Typ 5.0 Frequency tPLH Min TA = −40°C to +85°C Max Min 100 Units Max 120 MHz 5.0 2.5 6.5 11.5 2.0 12.5 ns 5.0 2.0 6.0 10.5 2.0 12.0 ns tPZH Output Enable Time 5.0 2.5 6.5 12.0 2.0 12.5 ns tPZL Output Enable Time 5.0 2.0 6.0 11.0 2.0 11.5 ns tPHZ Output Disable Time 5.0 1.5 7.0 12.5 1.0 13.5 ns tPLZ Output Disable Time 5.0 1.5 5.5 10.5 1.0 10.5 ns Note 4: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW CP Pulse Width HIGH or LOW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 1.0 3.5 4.0 ns 5.0 −1.0 1.0 1.5 ns 5.0 2.0 3.5 3.5 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 40.0 pF VCC = 5.0V www.fairchildsemi.com Units (Note 5) 4 Conditions 74ACT534 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 5 www.fairchildsemi.com 74ACT534 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com