74ACT563SC

74ACT563 Octal Latch with 3-STATE Outputs tm Features General Description ■ ICC and IOZ reduced by 50% ■ Inputs and outputs on opposite sides of package allow The ACT563 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. easy interface with microprocessors ■ Useful as input or output port for microprocessors ■ Functionally identical to ACT573 but with inverted The ACT563 device is functionally identical to the ACT573, but with inverted outputs. outputs ■ Outputs source/sink 24mA ■ ACT563 has TTL-compatible inputs Ordering Information Order Number Package Number 74ACT563SC M20B Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation. ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 74ACT563 Octal Latch with 3-STATE Outputs April 2007 Function Table The ACT563 contains eight D-type latches with 3-STATE complementary outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches. Inputs OE LE Internal Output D Q O Function H X X X Z High-Z H H L H Z High-Z H H H L Z High-Z H L X NC Z Latched L H L H H Transparent L H H L L Transparent L L X NC NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 2 74ACT563 Octal Latch with 3-STATE Outputs Functional Description Symbol VCC IIK Parameter Rating Supply Voltage –0.5V to +7.0V DC Input Diode Current VI = –0.5V –20mA VI = VCC + 0.5V +20mA VI DC Input Voltage IOK DC Output Diode Current –0.5V to VCC + 0.5V VO = –0.5V –20mA VO = VCC + 0.5V +20mA VO DC Output Voltage –0.5V to VCC + 0.5V IO DC Output Source or Sink Current ±50mA ICC or IGND DC VCC or Ground Current per Output Pin ±50mA TSTG Storage Temperature –65°C to +150°C TJ Junction Temperature 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage TA Operating Temperature ∆V / ∆t Rating 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns Minimum Input Edge Rate: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 3 74ACT563 Octal Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIH VIL VOH Parameter VCC (V) Conditions Typ. TA = –40°C to +85°C Guaranteed Limits VOUT = 0.1V or VCC – 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC – 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = –50µA 4.49 4.4 4.4 5.49 5.4 5.4 3.86 3.76 4.86 4.76 Minimum HIGH Level Input Voltage 5.5 Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage TA = +25°C 4.5 4.5 5.5 Units V V V VIN = VIL or VIH: 4.5 VOL Maximum LOW Level Output Voltage IOH = –24mA –24mA(1) 5.5 IOH = 4.5 IOUT = 50µA 5.5 0.001 0.1 0.1 0.001 0.1 0.1 0.36 0.44 0.36 0.44 V VIN = VIL or VIH: 4.5 IOL = 24mA 5.5 IOL = 24mA(1) IIN Maximum Input Leakage Current 5.5 VI = VCC, GND ±0.1 ±1.0 µA IOZ Maximum 3-STATE Current 5.5 VI = VIL, VIH; VO = VCC, GND ±0.25 ±2.5 µA ICCT Maximum ICC/Input 5.5 VI = VCC – 2.1V 1.5 mA IOLD Minimum Dynamic Output Current(2) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. –75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 40.0 µA IOHD ICC 0.6 4.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 4 74ACT563 Octal Latch with 3-STATE Outputs DC Electrical Characteristics TA = +25°C, CL = 50pF Symbol Parameter TA = –40°C to +85°C, CL = 50pF VCC (V)(3) Min. Typ. Max. Min. Max. Units tPLH Propagation Delay, Dn to On 5.0 3.0 7.0 11.5 2.5 12.5 ns tPHL Propagation Delay, Dn to On 5.0 3.0 6.0 10.0 2.5 11.0 ns tPLH Propagation Delay, LE to On 5.0 3.0 6.5 10.5 2.5 11.5 ns tPHL Propagation Delay, LE to On 5.0 2.5 5.5 9.5 2.0 10.5 ns tPZH Output Enable Time 5.0 2.5 5.5 9.0 2.0 10.0 ns tPZL Output Enable Time 5.0 2.0 5.5 8.5 2.0 9.5 ns tPHZ Output Disable Time 5.0 3.5 6.5 10.5 2.5 11.5 ns tPLZ Output Disable Time 5.0 2.0 4.5 8.0 1.0 8.5 ns Note: 3. Voltage range 5.0 is 5.0V ± 0.5V. AC Operating Requirements TA = +25°C, CL = 50pF Symbol Parameter VCC (V)(4) Typ. TA = –40°C to +85°C, CL = 50pF Guaranteed Minimum Units tS Setup Time, HIGH or LOW, Dn to LE 5.0 1.5 4.0 4.5 ns tH Hold Time, HIGH or LOW, Dn to LE 5.0 –2.0 0 0 ns tW LE Pulse Width, HIGH 5.0 2.0 3.0 3.0 ns Note: 4. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = OPEN 4.5 pF CPD Power Dissipation Capacitance VCC = 5.0V 50.0 pF ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 5 74ACT563 Octal Latch with 3-STATE Outputs AC Electrical Characteristics 74ACT563 Octal Latch with 3-STATE Outputs Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 2. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 6 ® ACEx Across the board. Around the world.¥ ActiveArray¥ Bottomless¥ Build it Now¥ CoolFET¥ CROSSVOLT¥ CTL™ Current Transfer Logic™ DOME¥ 2 E CMOS¥ ® EcoSPARK EnSigna¥ FACT Quiet Series™ ® FACT ® FAST FASTr¥ FPS¥ ® FRFET GlobalOptoisolator¥ GTO¥ HiSeC¥ i-Lo¥ ImpliedDisconnect¥ IntelliMAX¥ ISOPLANAR¥ MICROCOUPLER¥ MicroPak¥ MICROWIRE¥ MSX¥ MSXPro¥ OCX¥ OCXPro¥ ® OPTOLOGIC ® OPTOPLANAR PACMAN¥ POP¥ ® Power220 ® Power247 PowerEdge¥ PowerSaver¥ ® PowerTrench Programmable Active Droop¥ ® QFET QS¥ QT Optoelectronics¥ Quiet Series¥ RapidConfigure¥ RapidConnect¥ ScalarPump¥ SMART START¥ ® SPM STEALTH™ SuperFET¥ SuperSOT¥-3 SuperSOT¥-6 SuperSOT¥-8 SyncFET™ TCM¥ ® The Power Franchise ® TinyLogic TINYOPTO¥ TinyPower¥ TinyWire¥ TruTranslation¥ PSerDes¥ ® UHC UniFET¥ VCX¥ Wire¥ ™ TinyBoost¥ TinyBuck¥ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I24 ©1988 Fairchild Semiconductor Corporation 74ACT563 Rev. 1.2 www.fairchildsemi.com 7 74ACT563 Octal Latch with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.