74ACT574MTC

Revised November 1999 74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC/ACT574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D-type inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. ■ ICC and IOZ reduced by 50% The AC/ACT574 is functionally identical to the AC/ACT374 except for the pinouts. ■ Inputs and outputs on opposite sides of package allowing easy interface with microprocessors ■ Useful as input or output port for microprocessors ■ Functionally identical to AC/ACT374 ■ 3-STATE outputs for bus-oriented applications ■ Outputs source/sink 24 mA ■ ACT574 has TTL-compatible inputs Ordering Code: Order Number Package Number 74AC574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC574SJ 74AC574MTC MTC20 74AC574PC Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-01 74ACT574SJ M20D 74ACT574MTC MTC20 74ACT574PC N20A 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009910 www.fairchildsemi.com 74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs September 1988 74AC574 • 74ACT574 Functional Description Function Table The AC/ACT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Inputs OE CP D Internal Outputs Q ON Function H H L NC Z H H H NC Z Hold Hold     L L Z Load H H Z Load L L L Data Available H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC +0.5V VO = VCC +0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ±50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ±50 mA Per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC +0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = 25°C TA = −40°C to +85°C (V) Typ Guaranteed Limits 3.0 1.5 2.1 2.1 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 0.1 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA V IOH = −12 mA VIN = VIL or VIH IOH = −24 mA IOH IOH = −24 mA (Note 2) VOL Maximum LOW Level Output Voltage 3.0 0.002 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 V 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA IOUT = 50 µA VIN = VILor VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, VGND VO = VCC, GND Leakage Current IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V ICC (Note 4) Maximum Quiescent Supply Current 5.5 40.0 µA VIN = VCC or GND 4.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC574 • 74ACT574 Absolute Maximum Ratings(Note 1) 74AC574 • 74ACT574 DC Electrical Characteristics for ACT Symbol VIH VIL VOH Parameter TA = 25°C VCC TA = −40°C to +85°C (V) Typ Guaranteed Limits Minimum HIGH Level 4.5 1.5 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 2.0 2.0 Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VILor VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 V IOH = −24 mA IOH = −24 mA (Note 5) V IOUT = 50 µA V IOL = 24 mA VIN = VILor VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current µA VI = VCC, GND VI = VIL, VIH ±2.5 µA 1.5 mA VI = VCC − 2.1V 5.5 75 mA VOLD = 1.65V 5.5 −75 mA 5.5 ICCT Maximum ICC/Input 5.5 I]OLD Minimum Dynamic IOHD Output Current (Note 6) ICC Maximum Quiescent Supply Current ±0.25 IOL = 24 mA (Note 5) 0.6 5.5 4.0 40.0 µA VO = VCC, GND VOHD = 3.85V VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter VCC TA = +25°C (V) CL = 50 pF CL = 50 pF (Note 7) Min Maximum Clock 3.3 75 112 60 Frequency 5.0 95 153 85 Propagation Delay 3.3 3.5 8.5 13.5 3.5 15.0 CP to On 5.0 2.0 6.0 9.5 2.0 11.0 Propagation Delay 3.3 3.5 7.5 12.0 3.5 13.5 CP to On 5.0 2.0 5.5 8.5 2.0 9.5 Output Enable Time 3.3 2.5 7.0 11.0 2.5 12.0 5.0 2.0 5.0 8.5 2.0 9.0 3.3 3.0 6.5 10.5 3.0 11.5 5.0 2.0 5.0 8.0 1.5 9.0 3.3 3.5 7.5 12.0 2.5 13.0 5.0 2.0 6.0 9.5 1.5 10.5 3.3 2.0 5.5 9.0 1.5 10.0 5.0 1.0 4.5 7.5 1.0 8.5 Output Enable Time Output Disable Time Output Disable Time Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Typ TA = −40°C to +85°C Max Min Units Max MHz ns ns ns ns ns ns Symbol tS tH tW Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 8) Typ Set-Up Time, HIGH or LOW 3.3 0.5 2.5 3.0 Dn to CP 5.0 0 1.5 2.0 Hold Time, HIGH or LOW 3.3 −0.5 1.5 1.5 Dn to CP 5.0 0 1.5 1.5 CP Pulse Width 3.3 3.5 6.0 7.0 HIGH or LOW 5.0 2.0 4.0 5.0 Units Guaranteed Minimum ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay tPHL Propagation Delay CP to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 9) Min Typ Max Min 5.0 100 110 5.0 2.5 7.0 11.0 2.0 Units Max 85 ns 12.0 ns 5.0 2.0 6.5 10.0 1.5 11.0 ns tPZH Output Enable Time 5.0 2.0 6.4 9.5 1.5 10.0 ns tPZL Output Enable Time 5.0 2.0 6.0 9.0 1.5 10.0 ns tPHZ Output Disable Time 5.0 2.0 7.0 10.5 1.5 11.5 ns tPLZ Output Disable Time 5.0 2.0 5.5 8.5 1.5 9.0 ns CP to On Note 9: Voltage Range 5.0 is 5.0V ±0.5V AC Operating Requirements for ACT Symbol Parameter Set-Up Time, HIGH or LOW tS Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW CP Pulse Width HIGH or LOW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 10) Typ Guaranteed Minimum 5.0 1.5 2.5 ns 5.0 −0.5 1.0 ns 5.0 2.5 4.0 ns Units Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 40.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC574 • 74ACT574 AC Operating Requirements for AC 74AC574 • 74ACT574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 6 74AC574 • 74ACT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ Type II 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74AC574 • 74ACT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 8 74AC574 • 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com