74ACT825SC

Revised September 2000 74ACT825 8-Bit D-Type Flip-Flop General Description Features The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface. The ACT825 has noninverting outputs. ■ Outputs source/sink 24 mA ■ Inputs and outputs are on opposite sides ■ TTL compatible inputs Ordering Code: Order Number Package Number 74ACT825SC M24B 74ACT825MTC MTC24 74ACT825SPC N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D7 Data Inputs O0–O7 Data Outputs OE1, OE2, OE3 Output Enables EN Clock Enable CLR Clear CP Clock Input FACT is a trademark of Fairchild Semiconductor. © 2000 Fairchild Semiconductor Corporation DS009895 www.fairchildsemi.com 74ACT825 8-Bit D-Type Flip-Flop July 1988 74ACT825 Functional Description The ACT825 consists of eight D-type edge-triggered flipflops. These devices have 3-STATE outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs Internal Output Q O Function OE CLR EN H X L H X L H L CP   Dn L L Z High-Z H H Z High-Z X X X L Z Clear Clear L L X X X L L H H H X X NC Z Hold L H H X X NC NC Hold H H L L L Z Load H H Z Load L L L Load H H H Load H H L L H L L H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change      Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) −0.5V to VCC +0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA VCC @ 4.5V, 5.5V +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) 125 mV/ns VIN from 0.8V to 2.0V ± 50 mA DC VCC or Ground Current ± 50 mA Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol Parameter TA = 25°C VCC TA = −40°C to +85°C (V) Typ Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 VIL Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 VIH Units Conditions Guaranteed Limits V V V VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 5.5 ±0.5 V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current IOL = 24 mA ± 1.0 µA VI = VCC, GND ±5.0 µA 1.5 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC −2.1V ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 80 µA VIN = VCC or GND Supply Current 0.6 V 5.5 8.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT825 Absolute Maximum Ratings(Note 1) 74ACT825 AC Electrical Characteristics Symbol fMAX Parameter Maximum Clock Frequency Propagation Delay tPLH CP to On tPHL Propagation Delay CP to On tPHL Propagation Delay CLR to On tPZH Output Enable Time OE to On tPZL Output Enable Time OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 4) Min Typ Max 5.0 120 158 5.0 1.5 5.5 9.5 1.5 10.5 ns 5.0 2.0 5.5 9.5 1.5 10.5 ns 5.0 2.5 8.0 13.5 2.0 15.5 ns 5.0 1.5 6.0 10.5 1.5 11.5 ns 5.0 2.0 6.5 11.0 1.5 12.0 ns 5.0 1.5 6.5 11.0 1.5 12.0 ns 5.0 1.5 6.0 10.5 1.5 11.5 ns 109 MHz Note 4: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW tS EN to CP tH Hold Time, HIGH or LOW EN to CP tW CP Pulse Width HIGH or LOW tW CLR Pulse Width, LOW tREC CLR to CP Recovery Time VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 0.5 2.5 2.5 ns 5.0 0 2.5 2.5 ns 5.0 0 2.0 2.5 ns 5.0 0 1.0 1.0 ns 5.0 2.5 4.5 5.5 ns 5.0 3.0 5.5 5.5 ns 5.0 1.5 3.5 4.0 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 44 pF VCC = 5.0V www.fairchildsemi.com Units (Note 5) 4 Conditions 74ACT825 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74ACT825 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 74ACT825 8-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com