74ACT841SCX

Revised September 2000 74ACT841 10-Bit Transparent Latch with 3-STATE Outputs General Description Features The ACT841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The ACT841 is a 10-bit transparent latch, a 10-bit version of the ACT373. ■ ACT841 has TTL-compatible inputs ■ Outputs source/sink 24 mA ■ Non-inverting 3-STATE outputs Ordering Code: Order Number Package Number 74ACT841SC M24B 74ACT841MTC MTC24 74ACT841SPC N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.) Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D9 Data Inputs O0–O9 3-STATE Outputs OE Output Enable LE Latch Enable FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010156 www.fairchildsemi.com 74ACT841 10-Bit Transparent Latch with 3-STATE Outputs November 1988 74ACT841 Functional Description On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The ACT841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. Function Table Inputs Internal Output LE D Q O Function OE X X X X Z High Z H H L L Z High Z H H H H Z High Z H L X NC Z Latched L H L L L Transparent L H H H H Transparent L L X NC NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) 125 mV/ns VIN from 0.8V to 2.0V +20 mA VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150 °C Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 Units Conditions Guaranteed Limits V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current ICCT Maximum ICC/Input 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.5 ±5.0 µA 1.5 µA 5.5 0.6 V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 80.0 µA Supply Current 5.5 8.0 VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT841 Absolute Maximum Ratings(Note 1) 74ACT841 AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay Dn to On tPHL Propagation Delay Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On tPZH Output Enable Time OE to On tPZL Output Enable Time OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 4) Min Typ Max Min Max 5.0 2.0 5.5 9.5 2.0 10.0 ns 5.0 2.0 5.5 9.5 2.0 10.0 ns 5.0 2.0 5.5 9.0 2.0 10.0 ns 5.0 2.0 5.5 9.0 2.0 10.0 ns 5.0 2.0 5.5 9.5 2.0 10.5 ns 5.0 2.0 5.5 9.5 2.0 10.5 ns 5.0 2.0 6.0 10.5 2.0 11.0 ns 5.0 2.0 6.0 10.5 2.0 11.0 ns Note 4: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW Dn to LE tH Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH tW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 −0.5 0.5 1.0 ns 5.0 0.5 2.0 2.0 ns 5.0 2.0 3.5 3.5 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 44 pF VCC = 5.0V www.fairchildsemi.com Units (Note 5) 4 74ACT841 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74ACT841 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 74ACT841 10-Bit Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com