Revised May 2005
74ACTQ16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The ACTQ16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
■ Utilizes Fairchild FACT Quiet Series technology
The ACTQ16245 utilizes Fairchild Quiet Series¥ technology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series¥ features GTO¥ output control for superior performance.
■ Buffered Positive edge-triggered clock
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin output skew
■ Separate control logic for each byte
■ 16-bit version of the ACTQ374
■ Outputs source/sink 24 mA
■ Additional specs for Multiple Output Switching
■ Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
Package Number
74ACTQ16374SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Description
74ACTQ16374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin
Description
Names
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
I0–I15
Inputs
O0–O15
Outputs
FACT¥, FACT Quiet Series¥ and GTO¥ are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010935
www.fairchildsemi.com
74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
June 1991
74ACTQ16374
Functional Description
Truth Tables
The ACTQ16374 consists of sixteen edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
Inputs
CP1
OE1
I0–I7
O0–O7
L
H
H
L
L
L
L
L
X
(Previous)
X
H
X
Z
Inputs
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
2
Outputs
OE2
I8–I15
O8–O15
L
H
H
L
L
L
L
L
X
(Previous)
X
H
X
Z
CP2
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z HIGH Impedance
LOW-to-HIGH Transition
www.fairchildsemi.com
Outputs
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
Supply Voltage (VCC)
20 mA
20 mA
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
0V to VCC
40qC to 85qC
Minimum Input Edge Rate ('V/'t)
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
r 50 mA
65qC to 150qC
per Output Pin
0V to VCC
Output Voltage (VO)
Operating Temperature (TA)
20 mA
20 mA
0.5V to VCC 0.5V
r50 mA
DC VCC or Ground Current
Storage Temperature
4.5V to 5.5V
Input Voltage (VI)
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
(V)
TA
TA
40qC to 85qC
Guaranteed Limits
Minimum HIGH
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
VOUT
V
VOUT
V
V
24 mA (Note 2)
IOUT
Output Voltage
5.5
0.001
0.1
0.1
0.36
0.44
V
V
50 PA
VIN
VIL or VIH
IOL
24 mA
24 mA (Note 2)
5.5
0.36
0.44
5.5
r 0.5
r 5.0
PA
5.5
r 0.1
r 1.0
PA
IOL
VI
VCC, GND
1.5
mA
VI
VCC 2.1V
8.0
80.0
PA
VIN
75
mA
VOLD
1.65V Max
75
mA
VOHD
3.85V Min
VI
VIL, VIH
VO
Maximum Input Leakage Current
ICCT
Maximum ICC/Input
5.5
ICC
Maximum Quiescent Supply Current
5.5
IOLD
Minimum Dynamic
IOHD
Output Current (Note 3)
VOLP
Quiet Output Maximum
0.6
5.5
5.0
0.5
0.8
V
VCC, GND
VCC or GND
Figure 1, Figure 2
Dynamic VOL
Maximum Overshoot
50 PA
24 mA
V
Leakage Current
VOHP
IOUT
IOH
0.1
Minimum Dynamic VOL
0.1V
or VCC 0.1V
4.76
0.1
Quiet Output
0.1V
or VCC 0.1V
VIL or VIH
0.001
IIN
VOLV
Conditions
VIN
4.5
Maximum 3-STATE
Units
IOH
Maximum LOW
4.5
IOZ
25qC
Typ
(Note 5)(Note 6)
5.0
5.0
0.5
1.0
VOH 1.0 VOH 1.5
Figure 1, Figure 2
V
(Note 5)(Note 6)
V
Figure 1, Figure 2
(Note 4)(Note 6)
VOHV
Minimum VCC Droop
5.0
VOH 1.0 VOH 1.8
V
Figure 1, Figure 2
(Note 4)(Note 6)
VIHD
Minimum HIGH Dynamic Input Voltage Level
5.0
1.7
2.0
V
(Note 4)(Note 7)
VILD
Maximum LOW Dynamic Input Voltage Level
5.0
1.2
0.8
V
(Note 4)(Note 7)
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n 1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (VILD).
3
www.fairchildsemi.com
74ACTQ16374
Absolute Maximum Ratings(Note 1)
74ACTQ16374
AC Electrical Characteristics
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 8)
Min
TA
40qC to 85qC
CL
Typ
Max
Min
50 pF
fMAX
Maximum Clock Frequency
5.0
71
tPLH
Propagation Delay
5.0
3.1
5.3
7.9
3.1
8.4
tPHL
CP to On
3.0
5.1
7.3
3.0
7.8
tPZH
Output Enable Time
2.5
4.7
7.4
2.5
7.9
3.0
5.4
8.0
2.0
8.5
2.1
5.1
7.9
2.1
8.2
2.0
4.8
7.4
2.0
7.9
5.0
tPZL
tPHZ
Output Disable Time
5.0
tPLZ
Units
Max
67
MHz
ns
ns
ns
Note 8: Voltage Range 5.0 is 5.0V r 0.5V.
AC Operating Requirements
Symbol
tS
Parameter
Setup Time, HIGH or LOW
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Units
(Note 9)
Typ
Guaranteed Limits
5.0
0.7
3.0
3.0
ns
5.0
0.8
1.0
1.0
ns
5.0
1.5
5.0
5.0
ns
Input to Clock
tH
Hold Time, HIGH or LOW
Input to Clock
tW
CP Pulse Width,
HIGH or LOW
Note 9: Voltage Range 5.0 is 5.0V r 0.5V.
www.fairchildsemi.com
4
40qC to 85qC
TA
CL
Symbol
Parameter
50 pF
40qC to 85qC
TA
CL
16 Outputs Switching
(Note 10)
Min
Typ
Max
Min
Max
13.3
6.6
16.3
4.6
11.4
6.4
15.5
3.5
10.4
tPLH
Propagation Delay
tPHL
Data to Output
tPZH
Output Enable Time
3.8
10.9
Output Disable Time
3.4
8.5
3.1
8.1
4.7
tPZL
tPHZ
tPLZ
tOSHL
Pin to Pin Skew
(Note 12)
HL Data to Output
tOSLH
Pin to Pin Skew
(Note 12)
LH Data to Output
tOST
Pin to Pin Skew
(Note 12)
LH/HL Data to Output
250 pF
Units
(Note 11)
ns
(Note 13)
ns
(Note 14)
ns
1.3
ns
2.1
ns
4.0
ns
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST).
Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC
5.0V
CPD
Power Dissipation Capacitance
30
pF
VCC
5.0V
5
Conditions
www.fairchildsemi.com
74ACTQ16374
Extended AC Electrical Characteristics
74ACTQ16374
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/VOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
VILD and VIHD:
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500:.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
• Monitor one of the switching outputs using a 50: coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or step out a min of 2 ns. Oscillation is defined as noise on the output LOW level that
exceeds VIL limits, or on output HIGH levels that exceed
VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
• Next decrease the input HIGH voltage level on the, VIH,
until the output begins to oscillate or steps out a min of 2
ns. Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as V IHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
VOHV and VOLP are measured with respect to ground reference.
Input pulses have the following characteristics: f
tf 3 ns, skew 150 ps.
1 MHz, tr
3 ns,
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
www.fairchildsemi.com
6
74ACTQ16374
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7
www.fairchildsemi.com
74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
www.fairchildsemi.com
8
