74ACTQ18823MTDX

Revised November 1999 74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACTQ18823 contains eighteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP), Clear (CLR), Clock Enable (EN) and Output Enable (OE) are common to each byte and can be shorted together for full 18-bit operation. ■ Utilizes Fairchild’s FACT Quiet Series technology The ACTQ18823 utilizes Fairchild’s Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector for superior performance. ■ Separate control logic for each byte ■ Broadside pinout allows for easy board layout ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin output skew ■ Extra data width for wider address/data paths or buses carrying parity ■ Outputs source/sink 24 mA ■ Additional specs for Multiple Output Switching ■ Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number 74ACTQ18823SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Description 74ACTQ18823MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) CLRn Clear (Active LOW) ENn Clock Enable (Active LOW) CPn Clock Pulse Input I0–I17 Inputs O0–O17 Outputs FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010953 www.fairchildsemi.com 74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs September 1991 74ACTQ18823 Connection Diagram Functional Description The ACTQ18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock (CPn) and buffered Output Enable (OEn) are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLRn) and Clock Enable (ENn) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table (Note 1) Inputs OE CLR EN H X L H X L H L X CP Internal Output Q On Function   In L L Z High Z H H Z High Z X X L Z Clear Clear L L X X X L L H H H X X NC Z Hold L H H X X NC NC Hold H H L H H L L H L L H L H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial Z= High Impedance = LOW-to-HIGH Transition NC= No Change     L L Z Load H H Z Load L L L Load H H H Load  Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically. www.fairchildsemi.com 2 74ACTQ18823 Logic Diagrams Byte 1 (0:8) Byte 2 (9:17) 3 www.fairchildsemi.com 74ACTQ18823 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC +0.5V +20 mA Supply Voltage (VCC) −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) 125 mV/ns VIN from 0.8V to 2.0V −0.5V to VCC + 0.5V VCC @ 4.5V, 5.5V ± 50 mA DC Output Source/Sink Current (IO) 0V to VCC Output Voltage (VO) DC Output Diode Current (IOK) VO = −0.5V 4.5V to 5.5V Input Voltage (VI) DC VCC or Ground Current ± 50 mA Per Output Pin Junction Temperature +140°C PDIP/SOIC Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Storage Temperature ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 Units V V V Conditions VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH VOL V IOH = −24 mA IOH = −24 mA (Note 3) Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.5 ±5.0 µA ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC −2.1V 80.0 µA VIN = VCC or GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min V IOUT = 50 µA VIN = VIL or VIH IOZ Maximum 3-STATE Leakage Current V IOL = 24 mA IOL = 24 mA (Note 3) VI = VIL, VIH VO = VCC, GND IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 ICC Maximum Quiescent Supply Current 5.5 IOLD Minimum Dynamic IOHD Output Current (Note 4) VOLP Quiet Output Maximum Dynamic VOL 5.0 0.5 0.8 V (Note 6)(Note 7) VOLV Quiet Output Minimum Dynamic VOL 5.0 −0.5 −0.8 V (Note 6)(Note 7) VOHP Maximum Overshoot 5.0 VOH + 1.0 VOH + 1.5 V (Note 5)(Note 7) VOHV Minimum VCC Droop 5.0 VOH − 1.0 VOH − 1.8 V (Note 5)(Note 7) VIHD Minimum High Voltage Level 5.0 1.7 2.0 V (Note 5)(Note 8) VILD Maximum Low Dynamic Input Voltage Level 5.0 1.2 1.2 V (Note 5)(Note 8) 0.6 8.0 5.5 Note 3: All outputs loaded; thresholds associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Worst case package. Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW. Note 7: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH. Note 8: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). www.fairchildsemi.com 4 Symbol fMAX Parameter Maximum Clock Frequency tPHL Propagation Delay tPLH CPn to On tPHL Propagation Delay CLRn to On tPZL Output Enable Time VCC TA = +25°C (V) CL = 50 pF Output Disable Time CL = 50 pF (Note 9) Min 5.0 100 5.0 2.0 9.0 2.0 9.5 2.0 9.0 2.0 9.5 5.0 2.0 9.0 2.0 9.5 5.0 2.0 9.0 2.0 10.0 2.0 9.0 2.0 10.0 tPZH tPLZ TA = −40°C to +85°C 5.0 tPHZ Typ Max Min Units Max 90 MHz 1.5 7.0 1.5 7.5 1.5 8.0 1.5 8.5 ns ns ns ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 10) tS Setup Time, HIGH or LOW, Input to Clock tH Hold Time, HIGH or LOW, Input to Clock tS Setup Time, HIGH or LOW, Enable to Clock tH Hold Time, HIGH or LOW, Enable to Clock tW CPn Pulse Width, HIGH or LOW tW CLRn Pulse Width, HIGH or LOW tREC Recovery Time, CLRn to CPn Typ TA = −40°C to +85°C CL = 50 pF Units Guaranteed Minimum 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns 5.0 4.0 4.0 ns 5.0 6.0 6.0 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. 5 www.fairchildsemi.com 74ACTQ18823 AC Electrical Characteristics 74ACTQ18823 Extended AC Electrical Characteristics TA = −40°C to +85°C VCC = Com Symbol Parameter TA = −40°C to +85°C CL = 50 pF VCC = Com 16 Outputs Switching CL = 250 pF (Note 12) (Note 13) Min Typ Max Min Max tPLH Propagation Delay 5.2 6.5 7.6 7.0 9.8 tPHL CPn to On 5.3 6.5 7.8 6.8 10.0 tPHL Propagation Delay 5.2 7.5 CLRn to On tPZH Output Enable Time tPZL Output Disable Time tPHZ tPZL tOSHL 4.8 5.3 6.2 4.2 4.8 6.5 4.4 5.3 6.0 3.5 4.2 4.8 4.6 5.2 6.0 Pin to Pin Skew (Note 11) CPn to On tOSLH Pin to Pin Skew (Note 11) CPn to On tOSHL Pin to Pin Skew (Note 11) CLRn to Output tOST Pin to Pin Skew (Note 11) CPn to Output Units ns ns (Note 14) ns (Note 15) ns 1.0 ns 1.0 ns 1.0 ns 1.5 ns Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (il.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 15: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 95 pF VCC = 5.0V www.fairchildsemi.com 6 Conditions The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillator steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 7 www.fairchildsemi.com 74ACTQ18823 FACT Noise Characteristics 74ACTQ18823 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)