74ACTQ823SPC

Revised September 2000 74ACTQ823 Quiet Series 9-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The ACTQ823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACTQ823 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Inputs and outputs on opposite sides of package allow easy interface with microprocessors ■ Improved latch-up immunity ■ TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ823SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ823SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D8 Data Inputs O0–O8 Data Outputs OE Output Enable CLR Clear CP Clock Input EN Clock Enable FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010921 www.fairchildsemi.com 74ACTQ823 Quiet Series 9-Bit D-Type Flip-Flop with 3-STATE Outputs May 1991 74ACTQ823 Functional Description The ACTQ823 consists of nine D-type edge-triggered flipflops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs OE CLR EN H X L H X L H L X L L H L Output Q O Function   D CP Internal L L Z High Z H H Z High Z X X L Z Clear X X X L L Clear H H X X NC Z Hold H H NC NC Hold H H L Load H H L L H L L H     X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial L  X L L Z H H Z Load L L L Load H H H Load Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Minimum Input Edge Rate ∆V/∆t −20 mA VO = VCC + 0.5V 125 mV/ns VIN from 0.8V to 2.0V +20 mA DC Output Voltage (VO) −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) VO = −0.5V 4.5V to 5.5V Input Voltage (VI) VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) ± 50 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150 °C DC Latch-Up Source ± 300 mA or Sink Current Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics for ACTQ Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V VIN = VILor VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 IOH = −24 mA V IOH = −24 mA (Note 2) Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA 5.5 ± 0.5 ± 5.0 µA V IOUT = 50 µA V IOL = 24 mA VIN = VILor VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND ICCT Maximum 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 80.0 µA ICC/Input Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage 5.5 0.6 5.5 8.0 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V 5.0 1.9 2.2 V 3 VIN = VCC or GND Figure 1, Figure 2 (Note 4)(Note 5) Figure 1, Figure 2 (Note 4)(Note 5) (Note 4)(Note 6) www.fairchildsemi.com 74ACTQ823 Absolute Maximum Ratings(Note 1) 74ACTQ823 DC Electrical Characteristics for ACTQ Symbol Maximum LOW Level VILD TA = +25°C VCC Parameter Dynamic Input Voltage (Continued) (V) Typ 5.0 1.2 TA = −40°C to +85°C Units Conditions Guaranteed Limits 0.8 V (Note 4)(Note 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: PDIP package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL CP to On tPLH Propagation Delay tPHL CLR to On tPZH Output Enable Time tPZL OE to On tPHZ Output Disable Time tPLZ OE to On tOSLH Output to Output tOSHL Skew Dn to On (Note 8) VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 7) Min Typ Max Min Max 5.0 2.0 7.0 9.0 2.0 10.0 ns 5.0 2.0 7.0 9.0 2.0 10.0 ns 5.0 2.5 8.0 10.0 2.5 11.0 ns 5.0 1.0 6.0 8.0 1.0 9.0 ns 0.5 1.0 1.0 ns 5.0 Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW D to CP tH Hold Time, HIGH or LOW Dn to CP tS Setup Time, HIGH or LOW EN to CP tH Hold Time, HIGH or LOW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 0.5 3.0 3.0 ns 5.0 0 1.5 1.5 ns 5.0 0 3.0 3.0 ns ns 5.0 0 1.5 1.5 tW CP Pulse Width, HIGH or LOW 5.0 2.5 4.0 4.0 tW CLR Pulse Width, LOW 5.0 3.0 4.0 tREC CLR to CP 5.0 1.5 3.5 EN to CP Recovery Time 4.0 Capacitance Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 54 pF VCC = 5.0V www.fairchildsemi.com 4 ns ns Note 9: Voltage Range 5.0 is 5.0V ± 0.5V Symbol Units (Note 9) Conditions ns The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/V OHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition for active and enable. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V IL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ823 FACT Noise Characteristics 74ACTQ823 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74ACTQ823 Quiet Series 9-Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com