74ALVC16374GX

Revised May 2005 74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ 1.65V - 3.6V VCC supply operation The 74ALVC16374 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. 4.4 ns max for 2.3V to 2.7V VCC The 74ALVC16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 3.6V tolerant inputs and outputs ■ tPD 3.5 ns max for 3.0V to 3.6V VCC 7.8 ns max for 1.65V to 1.95V VCC ■ Power-off high impedance inputs and outputs ■ Supports live insertion and withdrawal (Note 1) ■ Uses patented noise/EMI reduction circuitry ■ Latchup conforms to JEDEC JED78 ■ ESD performance: Human body model ! 2000V Machine model ! 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74ALVC16374GX (Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74ALVC16374MTD (Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation DS500692 www.fairchildsemi.com 74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs October 2001 74ALVC16374 Logic Symbol Pin Descriptions Pin Names Connection Diagrams Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments Pin Assignment for TSSOP 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Inputs Pin Assignment for FBGA Outputs   OE1 I0–I7 O0–O7 L H H L L L L L X O0 X H X Z CP1 Inputs OE2 I8–I15 O8–O15 L H H L L L L L X O0 X H X Z CP2   H L X Z O0 (Top Thru View) www.fairchildsemi.com 2 Outputs HIGH Voltage Level LOW Voltage Level Immaterial (HIGH or LOW, inputs may not float) High Impedance Previous O0 before HIGH-to-LOW of CP flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. The 74ALVC16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagram Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ALVC16374 Functional Description 74ALVC16374 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 5) Recommended Operating Conditions (Note 6) 0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V Power Supply Operating DC Input Diode Current (IIK) VI  0V 0V to VCC 50 mA Output Voltage (VO) 0V to VCC 50 mA Minimum Input Edge Rate ('t/'V) DC Output Diode Current (IOK) Free Air Operating Temperature (TA) VO  0V DC Output Source/Sink Current VIN r50 mA (IOH/IOL) Supply Pin (I CC or GND) 0.8V to 2.0V, VCC 40qC to 85qC 3.0V 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VCC or GND Current per Storage Temperature Range (TSTG) 1.65V to 3.6V Input Voltage (VI) r100 mA 65qC to 150qC Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter VCC Conditions (V) HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Min 1.65 -1.95 0.65 x VCC 2.3 - 2.7 1.7 2.7 - 3.6 2.0 Max V 1.65 -1.95 0.35 x VCC 2.3 - 2.7 0.7 2.7 - 3.6 0.8 IOH 100 PA 1.65 - 3.6 VCC - 0.2 IOH 4 mA 1.65 1.2 IOH 6 mA 2.3 2 IOH 12 mA 2.3 1.7 2.7 2.2 Units V V 3.0 2.4 IOH 24 mA 3.0 2 IOL 100 PA 1.65 - 3.6 0.2 IOL 4 mA 1.65 0.45 IOL 6 mA 2.3 0.4 IOL 12mA 2.3 0.7 IOL 24 mA 2.7 0.4 3 0.55 V II Input Leakage Current 0 d VI d 3.6V 3.6 r5.0 PA IOZ 3-STATE Output Leakage 0 d VO d 3.6V 3.6 r10 PA ICC Quiescent Supply Current VI 3.6 40 PA 'ICC Increase in ICC per Input VIH 3 -3.6 750 PA www.fairchildsemi.com VCC or GND, IO VCC  0.6V 4 0 TA Symbol CL Parameter V CC Min fMAX Maximum Clock Frequency tPHL, tPLH Propagation Delay Bus to Bus 40qC to 85qC, RL 50 pF 3.3V r 0.3V V CC Max 2.7V Min 250 V CC Max 200 Min 500: CL 30 pF 2.5V r 0.2V V CC Max 1.8V r 0.15V Min 200 Units Max 100 ns 1.3 3.5 1.5 4.4 1.0 3.9 1.5 7.8 ns tPZL, tPZH Output Enable Time 1.3 4.0 1.5 5.1 1.0 4.6 1.5 9.2 ns tPLZ, tPHZ Output Disable Time 1.3 4.0 1.5 4.3 1.0 3.8 1.5 6.8 ns tW Pulse Width 1.5 1.5 1.5 4.0 ns tS Setup Time 1.5 1.5 1.5 2.5 ns tH Hold Time 1.0 1.0 1.0 1.0 ns Capacitance Symbol Parameter Conditions TA 25qC VCC Typical Units CIN Input Capacitance VI 0V or VCC 3.3 6 pF COUT Output Capacitance VI 0V or VCC 3.3 7 pF CPD Power Dissipation Capacitance 3.3 20 2.5 20 Outputs Enabled f 10 MHz, CL 5 50 pF pF www.fairchildsemi.com 74ALVC16374 AC Electrical Characteristics 74ALVC16374 AC Loading and Waveforms TABLE 1. TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VL tPZH, tPHZ GND FIGURE 1. AC Test Circuit TABLE 2. Symbol VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V 1.8V r 0.15V Vmi 1.5V 1.5V VCC/2 VCC/2 Vmo 1.5V 1.5V VCC/2 VCC/2 VX VOL  0.3V VOL  0.3V VOL  0.15V VOL  0.15V VY VOL  0.3V VOL  0.3V VOL  0.15V VOL  0.15V VL V6 6V VCC*2 VCC*2 FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms www.fairchildsemi.com 6 74ALVC16374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com 74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8