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74AUP1G57
TinyLogic® Low Power Universal Configurable TwoInput Logic Gate
Features
Description
0.8V to 3.6V VCC Supply Operation
High Speed tPD
- 2.9ns: Typical at 3.3V
Power-Off High-Impedance Inputs and Outputs
The 74AUP1G57 is a universal configurable 2-input
logic gate that provides a high performance and low
power solution ideal for battery-powered portable
applications. This product is designed for a wide low
voltage operating range (0.8V to 3.6V) and guarantees
very low static and dynamic power consumption across
the entire voltage range. All inputs are implemented
with hysteresis to allow for slower transition input
signals and better switching noise immunity.
Low Dynamic Power Consumption
- CPD=2.9pF Typical at 3.3V
Ultra-Small MicroPak™ Packages
3.6V Over-Voltage Tolerant I/Os at VCC
from 0.8V to 3.6V
Low Static Power Consumption
- ICC=0.9µA Maximum
The 74AUP1G57 provides for multiple functions as
determined by various configurations of the three
inputs. The potential logic functions provided are AND,
NAND, OR, NOR, and XNOR, inverter and buffer. Refer
to Figures 2 to 8.
Ordering Information
Part Number
Top Mark
Package
Packing Method
74AUP1G57L6X
AB
6-Lead Micropak™, 1.0mm Wide
5000 Units on
Tape & Reel
74AUP1G57FHX
AB
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
5000 Units on
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
www.fairchildsemi.com
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
October 2010
B
1
6
C
GND
2
5
VCC
A
3
4
Y
Figure 1. MicroPak™ (Top Through View)
Pin Definitions
Pin #
Name
1
B
2
GND
3
A
Data Input
4
Y
Output
5
VCC
6
C
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
Description
Data Input
Ground
Supply Voltage
Data Input
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Pin Configurations
www.fairchildsemi.com
2
Inputs
74AUP1G57
C
B
A
Y=Output
L
L
L
H
L
L
H
L
L
H
L
H
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
H
H
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
Function Selection Table
2-Input Logic Function
Connection Configuration
2-Input AND
Figure 2
2-Input AND with Both Inputs Inverted
Figure 5
2-Input NAND with Inverted Input
Figure 3, Figure 4
2-Input OR with Inverted Input
Figure 3, Figure 4
2-Input NOR
Figure 5
2-Input NOR with Both Inputs Inverted
Figure 2
2-Input XNOR
Figure 6
Inverter
Figure 7
Buffer
Figure 8
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Function Table
www.fairchildsemi.com
3
implementation is next to the board-level physical
implementation of how the pins of the function should
be connected.
Figure 2 through Figure 8 show the logical functions
that can be implemented using the 74AUP1G57. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
VCC
B
Y
C
B
B
B
Y
C
Figure 2.
VCC
1
6
2
5
3
4
C
Y
C
B
Y
Y
C
2-Input AND Gate or 2-Input NOR
with Both Inputs Inverted
B
Figure 3.
1
6
2
5
3
4
C
Y
2-Input NAND with Inverted B Input or
2-Input OR Gate with Inverted C Input
VCC
VCC
A
C
A
C
Figure 4.
A
Y
A
Y
1
6
2
5
3
4
Y
C
C
A
Y
2-Input NAND with Inverted C Input or
2-Input OR Gate with Inverted A Input
A
Y
C
Figure 5.
1
6
2
5
3
4
C
Y
2-Input NOR Gate or 2-Input AND Gate with
Both Inputs Inverted
VCC
VCC
B
B
C
Y
1
6
2
5
3
4
C
A
Y
A
Y
1
6
2
5
3
4
Y
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
74AUP1G57 Logic Configurations
Figure 7. Inverter
Figure 6. 2-Input XNOR Gate
VCC
B
Y
Figure 8.
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
B
1
6
2
5
3
4
Y
Non-Inverter Buffer
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage
VIN
DC Input Voltage
VOUT
IIK
IOK
IOH / IOL
ICC or IGND
TSTG
HIGH or LOW State
DC Output Voltage
(1)
VCC=0V
DC Input Diode Current
DC Output Diode Current
Min.
Max.
Unit
-0.5
4.6
V
-0.5
4.6
V
-0.5
VCC + 0.5
-0.5
4.6
VIN < 0V
-50
VOUT < 0V
-50
VOUT > VCC
+50
DC Output Source / Sink Current
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
-65
V
mA
mA
±50
mA
±50
mA
+150
°C
TJ
Junction Temperature Under Bias
+150
°C
TL
Junction Lead Temperature, Soldering 10s
+260
°C
PD
Power Dissipation at +85°C
ESD
MicroPak-6
130
MicroPak2-6
120
Human Body Model, JEDEC:JESD22-A114
5000+
Charged Device Model, JEDEC:JESD22-C101
2000
mW
V
Note:
1. IO absolute maximum rating must be observed.
Recommended Operating Conditions(2)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
Supply Voltage
VIN
Input Voltage
VOUT
IOH/IOL
Output Voltage
Output Current
TA
Operating Temperature, Free Air
θJA
Thermal Resistance
Conditions
Min.
Max.
Unit
0.8
3.6
V
V
0
3.6
VCC=0V
0
3.6
HIGH or LOW State
0
VCC
VCC=3.0V to 3.6V
±4.0
VCC=2.3V to 2.7V
±3.1
VCC=1.65V to 1.95V
±1.9
VCC=1.4V to 1.6V
±1.7
V
mA
VCC=1.1V to 1.3V
±1.1
VCC=0.8V
±20.0
µA
+85
°C
-40
MicroPak-6
500
MicroPak2-6
560
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Absolute Maximum Ratings
°C/W
Note:
2. Unused inputs must be held HIGH or LOW. They may not float.
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
www.fairchildsemi.com
5
Symbol
Parameter
VCC
Conditions
0.80
VP
VN
VH
Positive Threshold
Voltage
Negative
Threshold Voltage
Hysteresis Voltage
Min.
Max.
0.30
0.60
0.30
0.60
0.53
0.90
0.53
0.90
1.11
0.74
1.11
1.65
0.91
1.29
0.91
1.29
2.30
1.37
1.77
1.37
1.77
3.00
1.88
2.29
1.88
2.29
0.80
0.10
0.60
0.10
0.60
1.10
0.26
0.65
0.26
0.65
1.40
0.39
0.75
0.39
0.75
1.65
0.47
0.84
0.47
0.84
2.30
0.69
1.04
0.69
1.04
3.00
0.88
1.24
0.88
1.24
0.80
0.07
0.50
0.07
0.50
1.10
0.08
0.46
0.08
0.46
1.40
0.18
0.56
0.18
0.56
1.65
0.27
0.66
0.27
0.66
2.30
0.53
0.92
0.53
0.92
0.79
1.31
0.79
1.31
0.80 ≤ VCC ≤ 3.60 IOH=-20µA
VCC-0.1
VCC-0.1
1.10 ≤ VCC ≤ 1.30 IOH=-1.1mA
0.75 x VCC
0.70 x VCC
1.40 ≤ VCC ≤ 1.60 IOH=-1.7mA
1.11
1.03
HIGH Level Output 1.65 ≤ VCC ≤ 1.95 IOH=-1.9mA
Voltage
IOH=-2.3mA
2.30 ≤ VCC ≤ 2.70
IOH=-3.1mA
1.32
1.30
2.05
1.97
1.90
1.85
IOH=-2.7mA
2.72
2.67
IOH=-4.0mA
2.60
2.55
LOW Level Output
Voltage
Units
V
V
V
V
0.80 ≤ VCC ≤ 3.60 IOL=20µA
0.10
0.10
1.10 ≤ VCC ≤ 1.30 IOL=1.1mA
0.30 x VCC
0.30 x VCC
1.40 ≤ VCC ≤ 1.60 IOL=1.7mA
0.31
0.37
1.65 ≤ VCC ≤ 1.95 IOL=1.9mA
0.31
0.35
IOL=2.3mA
0.31
0.33
IOL=3.1mA
0.44
0.45
IOL=2.7mA
0.31
0.33
IOL=4.0mA
0.44
0.45
0 ≤ VIN ≤ 3.6
±0.1
±0.5
µA
0 ≤ (VIN,VO) ≤ 3.6
0.2
0.6
µA
VIN or VO=0V
to 3.6V
0.2
0.6
µA
VIN - VCC or GND
0.5
0.9
2.70 ≤ VCC ≤ 3.60
IOFF
Max.
0.74
2.30 ≤ VCC ≤ 2.70
IIN
Min.
1.40
3.00 ≤ VCC ≤ 3.60
VOL
TA=-40 to +85°C
1.10
3.00
VOH
TA=+25°C
Input Leakage
Current
Power Off Leakage
Current
0V to 3.6V
0V
ΔIOFF
Additional Power
Off Leakage
Current
0V to 0.2V
ICC
Quiescent Supply
Current
0.8V to 3.6V
ΔICC
Increase in ICC per
Input
3.3V
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
VCC ≤ VIN ≤ 3.6
VIN=VCC -0.6V
±0.9
40.0
50.0
V
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
DC Electrical Characteristics
µA
µA
www.fairchildsemi.com
6
Symbol
Parameter
VCC
Conditions
Min.
Max
Min.
Max.
1.10 ≤ VCC ≤ 1.30
2.5
6.5
12.6
2.5
13.0
1.40 ≤ VCC ≤ 1.60
2.2
4.6
7.6
2.2
8.2
2.0
3.9
6.2
2.0
6.8
2.30 ≤ VCC ≤ 2.70
1.7
3.1
4.5
1.7
5.1
3.00 ≤ VCC ≤ 3.60
1.3
2.9
3.9
1.3
4.1
1.65 ≤ VCC ≤ 1.95
CL=5pF, RL=1MΩ
0.80
Propagation
Delay
Typ.
Units
27.1
1.10 ≤ VCC ≤ 1.30
3.2
7.6
14.4
2.8
14.9
1.40 ≤ VCC ≤ 1.60 CL=10pF,
1.65 ≤ VCC ≤ 1.95 RL=1MΩ
2.6
5.3
8.7
2.8
9.3
2.2
4.6
7.0
2.2
7.8
2.30 ≤ VCC ≤ 2.70
1.9
3.7
5.2
1.9
5.9
3.00 ≤ VCC ≤ 3.60
1.3
2.8
4.6
1.3
4.9
0.80
32.6
1.10 ≤ VCC ≤ 1.30
3.4
8.3
15.7
3.1
16.7
1.40 ≤ VCC ≤ 1.60 CL=15pF,
1.65 ≤ VCC ≤ 1.95 RL=1MΩ
2.8
5.8
9.4
3.1
10.4
2.5
5.1
7.9
2.5
8.7
2.30 ≤ VCC ≤ 2.70
2.1
4.0
6.1
2.1
6.9
3.00 ≤ VCC ≤ 3.60
1.3
3.2
5.0
1.3
5.5
0.80
ns
25.4
1.10 ≤ VCC ≤ 1.30
3.4
8.6
18.5
3.4
19.0
1.40 ≤ VCC ≤ 1.60 CL=30pF,
1.65 ≤ VCC ≤ 1.95 RL=1MΩ
3.1
5.5
10.5
3.1
11.0
2.1
4.5
8.7
2.1
9.5
2.30 ≤ VCC ≤ 2.70
1.5
3.4
6.9
1.5
7.4
3.00 ≤ VCC ≤ 3.60
1.1
2.9
5.9
1.1
6.3
CIN
Input
Capacitance
0
0.8
pF
COUT
Output
Capacitance
0
1.7
pF
CPD
Power
Dissipation
Capacitance
0.80
1.8
1.10 ≤ VCC ≤ 1.30
1.82
1.40 ≤ VCC ≤ 1.60 VIN=0V or VCC,
1.65 ≤ V ≤ 1.95 f=10MHz
1.85
2.30 ≤ VCC ≤ 2.70
2.1
3.00 ≤ VCC ≤ 3.60
2.9
1.9
CC
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
Figure
22.1
0.80
tPHL, tPLH
TA=-40 to
+85°C
TA=+25°C
Figure 9
Figure 10
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
AC Electrical Characteristics
pF
www.fairchildsemi.com
7
Figure 9.
AC Test Circuit
Figure 10.
AC Waveforms
VCC
Symbol
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.10V
1.2V ± 0.10V
0.8V
Vmi
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
Vmo
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
AC Loadings and Waveforms
www.fairchildsemi.com
8
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Physical Dimensions
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.25
0.15 6X
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
Notes:
(0.13)
4X
BOTTOM VIEW
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 11.
6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
L6X
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
9
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Physical Dimensions
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
0.35
6
5
4
BOTTOM VIEW
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 12.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
10
74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
© 2008 Fairchild Semiconductor Corporation
74AUP1G57 • Rev. 1.0.4
www.fairchildsemi.com
11
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
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