Is Now Part of
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Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
74AUP1G95
TinyLogic® Low Power Universal Configurable
Two-Input Logic Gate (Open Drain Output)
Features
Description
0.8 V to 3.6 V VCC Supply Operation
Extremely High Speed tPD
- 3.2 ns: Typical at 3.3 V
Power-Off High-Impedance Inputs and Outputs
The 74AUP1G95 is a universal, configurable, two-input
logic gate with an open-drain output that provides a
high-performance and low-power solution for batterypowered portable applications. This product is
designed for a wide low voltage operating range (0.8 V
to 3.6 V) and guarantees very low static and dynamic
power consumption across the entire voltage range. All
inputs are implemented with hysteresis to allow for
slower transition input signals and better switching
noise immunity.
Low Dynamic Power Consumption
- CPD=3.0 pF Typical at 3.3 V
Ultra-Small MicroPak™ Packages
3.6 V Over-Voltage Tolerant I/Os at VCC
from 0.8V to 3.6 V
Low Static Power Consumption
- ICC=0.9 µA Maximum
The 74AUP1G95 provides for multiple functions, as
determined by various configurations of the three inputs.
The potential logic functions provided are MUX, AND,
OR, NAND, NOR, inverter, and buffer (see Figure 2
through Figure 8).
Ordering Information
Part Number
Top Mark
74AUP1G95L6X
AN
6-Lead, MicroPak™, 1.0 mm Wide
5000 Units on Tape & Reel
74AUP1G95FHX
AN
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
5000 Units on Tape & Reel
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
Package
Packing Method
www.fairchildsemi.com
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
September 2012
B
1
6
C
GND
2
5
VCC
A
3
4
Y
Figure 1.
MicroPak™ (Top Through View)
Pin Definitions
Pin #
Name
Description
1
B
Data Input
2
GND
Ground
3
A
Data Input
4
Y
Output (Open Drain)
5
VCC
Supply Voltage
6
C
Data Input
Function Table
Inputs
Y=Output
C
B
A
L
L
L
L
L
L
H
L
L
H
L
H(1
L
H
H
H(1)
H
L
L
L
H
L
H
H(1)
H
H
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
H
H(1)
Note:
1. High impedance output state, open drain.
Function Selection Table
2-Input Logic Function
Connection Configuration
2-to-1 MUX
Figure 2
2-Input AND Gate
Figure 3
2-Input OR Gate with One Inverted Input
Figure 4
2-Input NAND Gate with One Inverted Input
Figure 4
2-Input AND Gate with One Inverted Input
Figure 5
2-Input NOR Gate with One Inverted Input
Figure 5
2-Input OR Gate
Figure 6
Inverted
Figure 7
Buffer
Figure 8
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Pin Configuration
www.fairchildsemi.com
2
implementation is next to the board-level physical
implementation of how the pins should be connected.
Figure 2 through Figure 8 show the logical functions that
can be implemented using the 74AUP1G95. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
VCC
VCC
C
B
B
Y
A
A
1
6
2
5
3
4
C
C
Y
Y
A
A
GND
Notes:
2. When C is L, Y=B.
3. When C is H, Y=A.
Figure 2.
1
6
2
5
3
4
C
Y
GND
2-to-1 MUX
Figure 3.
2-Input AND Gate
VCC
VCC
C
C
Y
B
Y
A
B
C
Y
A
A
1
6
2
5
3
4
C
C
Y
B
1
6
2
5
3
4
C
Y
Y
GND
GND
Figure 4.
2-Input OR Gate with One Inverted
Input
2-Input NAND Gate with One Inverted Input
Figure 5.
2-Input AND Gate with One Inverted
Input
2-Input NOR Gate with One Inverted Input
VCC
VCC
C
B
Y
B
1
6
2
5
3
4
C
C
Y
Y
GND
Figure 6.
GND
Figure 7.
2-Input OR Gate
VCC
B
B
Y
1
6
2
5
3
4
1
6
2
5
3
4
Inverter
C
Y
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Logic Configurations
Y
GND
Figure 8.
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
Buffer
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply Voltage
-0.5
4.6
V
VIN
DC Input Voltage
-0.5
4.6
V
DC Output Voltage
-0.5
4.6
V
VOUT(2)
IIK
DC Input Diode Current
VIN < 0 V
-50
mA
IOK
DC Output Diode Current
VOUT < 0 V
-50
mA
IOL
DC Output Sink Current
+50
mA
ICC or IGND
TSTG
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
-65
±50
mA
+150
°C
TJ
Junction Temperature Under Bias
+150
°C
TL
Junction Lead Temperature, Soldering 10s
+260
°C
PD
Power Dissipation at +85°C
MicroPak™-6
130
MicroPak2™-6
ESD
mW
120
Human Body Model, JEDEC:JESD22-A114
4000
Charged Device Model, JEDEC:JESD22-C101
2000
V
Note:
2. IO absolute maximum rating must be observed.
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Condition
Min.
Max.
Unit
0.8
3.6
V
VCC
Supply Voltage
VIN
Input Voltage
0
3.6
V
Output Voltage
0
3.6
V
VOUT
IOL
Output Current
TA
Operating Temperature, Free Air
θJA
Thermal Resistance
VCC=3.0 V to 3.6 V
±4.0
VCC=2.3 V to 2.7 V
±3.1
VCC=1.65 V to 1.95 V
±1.9
VCC=1.4 V to 1.6 V
±1.7
VCC=1.1 V to 1.3 V
±1.1
VCC=0.8 V
±20.0
µA
+85
°C
-40
MicroPak™-6
500
MicroPak2™-6
560
mA
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Absolute Maximum Ratings
°C/W
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
www.fairchildsemi.com
4
Symbol
VP
VN
VH
VOL
IIN
Parameter
VCC
Positive
Threshold
Voltage
Negative
Threshold
Voltage
Hysteresis
Voltage
LOW Level
Output
Voltage
TA=25°C
TA=-40 to 85°C
Min.
Max.
Min.
Max.
0.80
0.30
0.60
0.30
0.60
1.10
0.53
0.90
0.53
0.90
1.40
0.74
1.11
0.74
1.11
1.65
0.91
1.29
0.91
1.29
2.30
1.37
1.77
1.37
1.77
3.00
1.88
2.29
1.88
2.29
0.80
0.10
0.60
0.10
0.60
1.10
0.26
0.65
0.26
0.65
1.40
0.39
0.75
0.39
0.75
1.65
0.47
0.84
0.47
0.84
2.30
0.69
1.04
0.69
1.04
3.00
0.88
1.24
0.88
1.24
0.80
0.07
0.50
0.07
0.50
1.10
0.08
0.46
0.08
0.46
1.40
0.18
0.56
0.18
0.56
1.65
0.27
0.66
0.27
0.66
2.30
0.53
0.92
0.53
0.92
3.00
0.79
1.31
0.79
1.31
Unit
V
V
V
0.80 ≤ VCC ≤ 3.60 IOL=20 µA
0.10
0.10
1.10 ≤ VCC ≤ 1.30 IOL=1.1 mA
0.30 x
VCC
0.30 x
VCC
1.40 ≤ VCC ≤ 1.60 IOL=1.7 mA
0.31
0.37
1.65 ≤ VCC ≤ 1.95 IOL=1.9 mA
0.31
0.35
2.30 ≤ VCC ≤ 2.70 IOL=3.1 mA
0.44
0.45
2.70 ≤ VCC ≤ 3.60 IOL=4.0 mA
0.44
0.45
0 ≤ VIN ≤ 3.6 V
±0.1
±0.5
µA
0 ≤ (VIN,VO)
≤ 3.6 V
0.2
0.6
µA
VIN or VO=0 V
to 3.6 V
0.2
0.6
µA
VIN - VCC or GND
0.5
0.9
Input
Leakage
Current
0V to 3.6V
IOFF
Power Off
Leakage
Current
0V
ΔIOFF
Additional
Power Off
Leakage
Current
0V to 0.2V
ICC
Quiescent
Supply
Current
0.8V to 3.6V
ΔICC
Condition
Increase in
ICC per Input
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
3.3V
VCC ≤ VIN ≤ 3.6 V
VIN=VCC -0.6 V
±0.9
40.0
50.0
V
µA
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
DC Electrical Characteristics
µA
www.fairchildsemi.com
5
Symbol
Parameter
VCC
Condition
TA=25°C
Min.
1.10 ≤ VCC ≤ 1.30
Propagation
Delay
Max.
Min.
Max
Unit
30
0.80
tPZL, tPLZ
Typ.
TA=-40 to 85°C
CL=15 pF,
1.40 ≤ VCC ≤ 1.60 RU=RD=5 KΩ
1.65 ≤ VCC ≤ 1.95 VI = 2 x (VCC)
(see Figure 9)
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
1.0
10.1
18.9
1.0
19.9
1.0
6.6
11.4
1.0
12.2
1.0
6.3
8.7
1.0
9.7
1.0
4.7
6.9
1.0
7.5
1.0
4.6
6.8
1.0
7.4
CIN
Input
Capacitance
0
0.8
pF
COUT
Output
Capacitance
0
1.7
pF
0.80
3.0
1.10 ≤ VCC ≤ 1.30
3.1
1.40 ≤ VCC ≤ 1.60 VIN=0 V or VCC,
1.65 ≤ VCC ≤ 1.95 f=10 MHz
3.2
2.30 ≤ VCC ≤ 2.70
3.8
3.00 ≤ VCC ≤ 3.60
4.4
CPD
Power
Dissipation
Capacitance
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
3.4
pF
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
AC Electrical Characteristics
www.fairchildsemi.com
6
Notes:
4. CL includes load and stray capacitance.
5. Input PRR = 1.0 MHz, tW = 500 ns.
Symbol
Figure 9.
AC Test Circuit
Figure 10.
AC Waveforms
VCC
3.3 V ± 0.3 V 2.5 V ± 0.2 V
1.8 V ± 0.15 V
1.5 V ± 0.10 V
1.2 V ± 0.10 V
0.8 V
Vmi
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
Vmo
VOL + 0.3 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.1 V
VOL + 0.1 V
VOL + 0.1 V
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
AC Loadings and Waveforms
www.fairchildsemi.com
7
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
0.25
0.15 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
BOTTOM VIEW
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 11.
6-Lead, MicroPak™, 1.0 mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
L6X
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
Tape Section
Cavity Number
Leader (Start End)
125 (Typical)
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Physical Dimensions
Cavity Status Cover Type Status
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
8
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
6
5
4
0.35
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 12.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
Tape Section
Cavity Number
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
Physical Dimensions
Cavity Status Cover Type Status
www.fairchildsemi.com
9
74AUP1G95 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)
10
www.fairchildsemi.com
© 2008 Fairchild Semiconductor Corporation
74AUP1G95 • Rev. 1.0.1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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