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74AUP1G98
TinyLogic® Low Power Universal Configurable
Two-Input Logic Gate
Features
Description
0.8V to 3.6V VCC Supply Operation
High Speed tPD
- 3.0ns: Typical at 3.3V
Power-Off High-Impedance Inputs and Outputs
The 74AUP1G98 is a universal configurable 2-input
logic gate that provides a high performance and low
power solution ideal for battery-powered portable
applications. This product is designed for a wide low
voltage operating range (0.8V to 3.6V) and guarantees
very low static and dynamic power consumption across
the entire voltage range. All inputs are implemented with
hysteresis to allow for slower transition input signals and
better switching noise immunity.
3.6V Over-Voltage Tolerant I/Os at VCC
from 0.8V to 3.6V
Low Static Power Consumption
- ICC=0.9µA Maximum
Low Dynamic Power Consumption
- CPD=2.5pF Typical at 3.3V
Ultra-Small MicroPak™ Packages
The 74AUP1G98 provides for multiple functions as
determined by various configurations of the three inputs.
The potential logic functions provided are MUX, AND,
OR, NAND, and NOR, inverter and buffer. Refer to
Figures 5 to 11.
Ordering Information
Part Number
Top Mark
Package
Packing Method
74AUP1G98L6X
AE
6-Lead Micropak™, 1.0mm Wide
5000 Units on
Tape & Reel
74AUP1G98FHX
AE
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
5000 Units on
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
October 2010
3
A
4
1
B
Y
6
C
Figure 1. Logic Diagram (Positive Logic)
Pin Configurations
B
1
6
C
GND
2
5
VCC
A
3
4
Y
Figure 2. MicroPak™ (Top Through View)
Pin Definitions
Pin # MicroPak™
Name
Description
1
B
2
GND
3
A
Data Input
4
Y
Output
5
VCC
6
C
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
Data Input
Ground
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Logic Diagram
Supply Voltage
Data Input
www.fairchildsemi.com
2
Inputs
C
B
L
L
74AUP1G98
A
Y=Output
L
L
H
L
H
H
L
H
L
L
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
H = HIGH Logic Level
L = LOW Logic Level
Function Selection Table
2-Input Logic Function
Connection Configuration
2-to-1 MUX with Inverted Output
Figure 3
2-Input NAND Gate
Figure 4
2-Input NOR Gate with One Inverted Input
Figure 5
2-Input AND Gate with One Inverted Input
Figure 5
2-Input NAND Gate with One Inverted Input
Figure 6
2-Input OR Gate with One Inverted Input
Figure 6
2-Input NOR Gate
Figure 7
Buffer
Figure 8
Inverter
Figure 9
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Function Table
www.fairchildsemi.com
3
Figure 3 through Figure 9 show the logical functions that
can be implemented using the 74AUP1G98. The
diagrams show the DeMorgan’s equivalent logic duals
for a given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should be
connected.
VCC
VCC
C
B
B
Y
A
A
1
6
2
5
3
4
C
C
Y
Y
A
A
GND
Note:
1. When C is L, Y=B.
2. When C is H, Y=A.
Figure 3. 2-to-1 MUX with Inverted Output
1
6
2
5
3
4
C
Y
GND
Figure 4.
2-Input NAND Gate
VCC
C
A
C
A
VCC
C
Y
Y
B
Y
A
1
6
2
5
3
4
B
C
C
Y
B
6
2
5
3
4
C
Y
Y
GND
Figure 5.
1
GND
Input NOR Gate with One Inverted Input Figure 6.
2-Input AND Gate with One Inverted Input
2-Input NAND Gate with One Inverted Input
2-Input OR Gate with One Inverted Input
VCC
VCC
C
B
Y
B
1
6
2
5
3
4
C
C
Y
Y
GND
1
6
2
5
3
4
C
Y
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
74AUP1G98 Logic Configurations
GND
Figure 8.
Figure 7. 2-Input NOR Gate
Buffer
VCC
B
B
Y
1
6
2
5
3
4
Y
GND
Figure 9.
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
Inverter
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage
VIN
DC Input Voltage
IIK
IOK
IOH / IOL
ICC or IGND
TSTG
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
Max.
Unit
-0.5
4.6
V
V
-0.5
4.6
HIGH or LOW State
-0.5
VCC + 0.5
VCC=0V
-0.5
4.6
(3)
VOUT
Min.
VIN < 0V
-50
VOUT < 0V
-50
VOUT > VCC
+50
DC Output Source / Sink Current
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
-65
V
mA
mA
±50
mA
±50
mA
+150
°C
TJ
Junction Temperature Under Bias
+150
°C
TL
Junction Lead Temperature, Soldering 10s
+260
°C
MicroPak-6
130
mW
MicroPak2-6
120
Power Dissipation at +85°C
ESD
Human Body Model, JEDEC:JESD22-A114
5000+
Charged Device Model, JEDEC:JESD22-C101
2000
V
Note:
3. IO absolute maximum rating must be observed.
Recommended Operating Conditions(4)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
Supply Voltage
VIN
Input Voltage
VOUT
IOH/IOL
TA
Output Voltage
Output Current
Conditions
Max.
Unit
0.8
3.6
V
V
0
3.6
VCC=0V
0
3.6
HIGH or LOW State
0
VCC
VCC=3.0V to 3.6V
±4.0
VCC=2.3V to 2.7V
±3.1
VCC=1.65V to 1.95V
±1.9
VCC=1.4V to 1.6V
±1.7
V
mA
VCC=1.1V to 1.3V
±1.1
VCC=0.8V
±20.0
µA
+85
°C
Operating Temperature, Free Air
Thermal Resistance
Min.
-40
MicroPak-6
500
MicroPak2-6
560
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Absolute Maximum Ratings
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
5
Symbol
VP
VN
VH
VOH
Parameter
VCC
Positive Threshold
Voltage
Negative
Threshold Voltage
Hysteresis Voltage
TA=-40 to 85°C
Max.
Min.
0.30
0.60
0.30
0.60
0.53
0.90
0.53
0.90
1.40
0.74
1.11
0.74
1.11
1.65
0.91
1.29
0.91
1.29
2.30
1.37
1.77
1.37
1.77
3.00
1.88
2.29
1.88
2.29
0.80
0.10
0.60
0.10
0.60
1.10
0.26
0.65
0.26
0.65
1.40
0.39
0.75
0.39
0.75
1.65
0.47
0.84
0.47
0.84
2.30
0.69
1.04
0.69
1.04
3.00
0.88
1.24
0.88
1.24
0.80
0.07
0.50
0.07
0.50
1.10
0.08
0.46
0.08
0.46
1.40
0.18
0.56
0.18
0.56
1.65
0.27
0.66
0.27
0.66
2.30
0.53
0.92
0.53
0.92
3.00
0.79
1.31
0.79
1.31
0.80 ≤ VCC ≤ 3.60
IOH=-20µA
VCC-0.1
VCC-0.1
1.10 ≤ VCC ≤ 1.30
IOH=-1.1mA
0.75 x VCC
0.70 x VCC
1.40 ≤ VCC ≤ 1.60
IOH=-1.7mA
1.11
1.03
HIGH Level Output 1.65 ≤ VCC ≤ 1.95
Voltage
2.30 ≤ VCC ≤ 2.70
IOH=-1.9mA
1.32
1.30
IOH=-2.3mA
2.05
1.97
IOH=-3.1mA
1.90
1.85
IOH=-2.7mA
2.72
2.67
IOH=-4.0mA
2.60
2.55
LOW Level Output
Voltage
Max.
0.80
0.80 ≤ VCC ≤ 3.60
IOL=20µA
0.10
0.10
IOL=1.1mA
0.30 x VCC
0.30 x VCC
1.40 ≤ VCC ≤ 1.60
IOL=1.7mA
0.31
0.37
1.65 ≤ VCC ≤ 1.95
IOL=1.9mA
0.31
0.35
IOL=2.3mA
0.31
0.33
IOL=3.1mA
0.44
0.45
V
V
V
IOL=2.7mA
0.31
0.33
0.44
0.45
0 ≤ VIN ≤ 3.6
±0.1
±0.5
µA
0V
0 ≤ (VIN,VO)≤ 3.6
0.2
0.6
µA
VIN or VO=0V to
3.6V
0.2
0.6
µA
VIN - VCC or GND
0.5
0V to 3.6V
IOFF
Power Off Leakage
Current
ΔIOFF
Additional Power
Off Leakage
Current
0V to 0.2V
ICC
Quiescent Supply
Current
0.8V to 3.6V
ΔICC
Increase in ICC per
Input
3.3V
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
V
IOL=4.0mA
2.70 ≤ VCC ≤ 3.60
Input Leakage
Current
Units
V
1.10 ≤ VCC ≤ 1.30
2.30 ≤ VCC ≤ 2.70
IIN
TA=25°C
Min.
1.10
3.00 ≤ VCC ≤ 3.60
VOL
Conditions
VCC ≤ VIN ≤ 3.6
VIN=VCC -0.6V
0.9
±0.9
40.0
50.0
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
DC Electrical Characteristics
µA
µA
www.fairchildsemi.com
6
Symbol
Parameter
VCC
Min.
0.80
Max.
Min.
Max.
2.9
8.7
12.9
2.7
13.2
1.40 ≤ VCC ≤ 1.60
2.4
5.1
7.7
2.4
8.3
CL=5pF, RL=1MΩ
2.2
4.4
6.3
1.9
7.0
2.30 ≤ VCC ≤ 2.70
2.0
3.5
4.8
1.8
5.4
3.00 ≤ VCC ≤ 3.60
1.5
3.1
4.2
1.5
4.5
26.7
1.10 ≤ VCC ≤ 1.30
3.3
8.5
14.5
3.0
15.1
1.40 ≤ VCC ≤ 1.60
2.7
5.8
8.8
2.8
9.5
2.5
4.7
7.2
2.3
8.0
2.30 ≤ VCC ≤ 2.70
1.9
3.6
5.3
1.9
5.9
3.00 ≤ VCC ≤ 3.60
1.5
3.1
4.7
1.5
4.9
1.65 ≤ VCC ≤ 1.95
CL=10pF,
RL=1MΩ
29.8
0.80
1.10 ≤ VCC ≤ 1.30
3.6
9.9
16.1
3.3
16.9
1.40 ≤ VCC ≤ 1.60
3.0
6.2
9.7
3.1
10.5
2.8
5.3
7.9
2.5
8.9
2.30 ≤ VCC ≤ 2.70
2.5
4.1
5.9
2.5
6.6
3.00 ≤ VCC ≤ 3.60
1.7
3.3
5.2
1.7
5.5
1.65 ≤ VCC ≤ 1.95
CL=15pF,
RL=1MΩ
ns
27.5
0.80
1.10 ≤ VCC ≤ 1.30
3.4
9.1
18.5
3.4
19.0
1.40 ≤ VCC ≤ 1.60
3.1
5.7
10.5
3,1
11.0
2.7
4.7
8.7
2.7
9.5
2.30 ≤ VCC ≤ 2.70
1.7
3.5
6.5
1.7
7.1
3.00 ≤ VCC ≤ 3.60
1.3
3.0
5.6
1.3
6.3
1.65 ≤ VCC ≤ 1.95
Units Figure
25.3
0.80
tPHL, tPLH
Typ.
1.10 ≤ VCC ≤ 1.30
1.65 ≤ VCC ≤ 1.95
Propagation
Delay
TA=-40 to 85°C
TA=25°C
Conditions
CL=30pF,
RL=1MΩ
CIN
Input
Capacitance
0
2.1
pF
COUT
Output
Capacitance
0
3.0
pF
0.80
1.7
1.10 ≤ VCC ≤ 1.30
1.8
CPD
Power
Dissipation
Capacitance
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
1.81
VIN=0V or VCC,
f=10MHz
1.84
2.30 ≤ VCC ≤ 2.70
2.1
3.00 ≤ VCC ≤ 3.60
2.5
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
Figure 10
Figure 11
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
AC Electrical Characteristics
pF
www.fairchildsemi.com
7
Figure 10.
AC Test Circuit
Figure 11.
AC Waveforms
VCC
Symbol
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ±
0.15V
1.5V ±
0.10V
1.2V ±
0.10V
0.8V
Vmi
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
Vmo
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
AC Loadings and Waveforms
www.fairchildsemi.com
8
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Physical Dimensions
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
0.25
0.15 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
Notes:
BOTTOM VIEW
(0.13)
4X
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 12.
6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
L6X
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
9
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
Physical Dimensions
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
6
0.35
5
4
BOTTOM VIEW
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 13.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
10
74AUP1G98 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate
© 2008 Fairchild Semiconductor Corporation
74AUP1G98 • Rev. 1.0.4
www.fairchildsemi.com
11
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
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