74F169SJX

Revised September 2000 74F169 4-Stage Synchronous Bidirectional Counter General Description Features The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. ■ Asynchronous counting and loading ■ Built-in lookahead carry capability ■ Presettable for programmable operation Ordering Code: Order Number Package Number Package Description 74F169SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F169SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F169PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009488 www.fairchildsemi.com 74F169 4-Stage Synchronous Bidirectional Counter April 1988 74F169 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL CEP Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CET Count Enable Trickle Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PE Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA U/D Up-Down Count Control Input 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA TC Terminal Count Output (Active LOW) 50/33.3 −1 mA/20 mA Functional Description Mode Select Table The 74F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0–P3 inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 for the 74F169 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). PE 3. Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET 2 Clock Edge X X X Load (Pn → Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) State Diagram 1. Count Enable = CEP • CET • PE Action on Rising L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 2. Up: (74F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET www.fairchildsemi.com CEP CET U/D 74F169 Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F169 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 µA 0.0 mA Max Output HIGH Voltage VOL Output LOW 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage VOH 2.0 Units VIH 10% VCC Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage 3.75 Circuit Current IIL −0.6 Input LOW Current −1.2 IOS Output Short-Circuit Current ICCL Power Supply Current www.fairchildsemi.com −60 35 4 Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (except CET) VIN = 0.5V (CET) −150 mA Max VOUT = 0V 52 mA Max VO = LOW 74F169 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min 60 Max fMAX Maximum Count Frequency 90 tPLH Propagation Delay 3.0 tPHL CP to Qn (PE HIGH or LOW) 4.0 9.0 11.5 4.0 16.0 4.0 13.0 tPLH Propagation Delay 5.5 12.0 15.5 5.5 20.0 5.5 17.5 tPHL CP to TC 4.0 8.5 12.5 4.0 15.0 4.0 13.0 tPLH Propagation Delay 2.5 4.5 6.5 2.5 9.0 2.5 7.0 tPHL CET to TC 2.5 8.5 11.0 2.5 12.0 2.5 12.0 tPLH Propagation Delay 3.5 8.5 11.5 3.5 16.0 3.5 12.5 tPHL U/D to TC 4.0 8.0 12.0 4.0 14.0 4.0 13.0 6.5 8.5 70 3.0 12.0 Units MHz 3.0 9.5 ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.0 4.5 4.5 tS(L) Pn to CP 4.0 4.5 4.5 tH(H) Hold Time, HIGH or LOW 3.0 3.5 3.5 tH(L) Pn to CP 3.0 3.5 3.5 tS(H) Setup Time, HIGH or LOW 7.0 8.0 8.0 tS(L) CEP or CET to CP 5.0 8.0 6.5 tH(H) Hold Time, HIGH or LOW 0 0 0 0.5 tH(L) CEP or CET to CP 0.5 1.0 tS(H) Setup Time, HIGH or LOW 8.0 10.0 9.0 tS(L) PE to CP 8.0 10.0 9.0 tH(H) Hold Time, HIGH or LOW 1.0 1.0 1.0 tH(L) PE to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 11.0 14.0 12.5 tS(L) U/D to CP 7.0 12.0 8.5 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) U/D to CP 0 0 0 tW(H) CP Pulse Width 4.0 6.0 4.5 tW(L) HIGH or LOW 7.0 9.0 8.0 5 Units Max ns ns ns ns ns www.fairchildsemi.com 74F169 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 74F169 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74F169 4-Stage Synchronous Bidirectional Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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