74F194PC

Revised January 2004 74F194 4-Bit Bidirectional Universal Shift Register General Description Features The 74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. ■ Typical shift frequency of 150 MHz ■ Asynchronous master reset ■ Hold (do nothing) mode ■ Fully synchronous serial or parallel data transfers Ordering Code: Order Number Package Number Package Description 74F194SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74F194PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2004 Fairchild Semiconductor Corporation DS009498 www.fairchildsemi.com 74F194 4-Bit Bidirectional Universal Shift Register April 1988 74F194 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0, S1 Mode Control Inputs 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA DSR Serial Data Input (Shift Right) 1.0/1.0 20 µA/−0.6 mA DSL Serial Data Input (Shift Left) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Parallel Outputs 50/33.3 −1 mA/20 mA Functional Description Mode Select Table The 74F194 contains four edge-triggered D-type flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data (P0–P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. Operating Mode Inputs Outputs MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X L Hold H l l X X X q0 q1 q2 q3 Shift Left H h l X l X q1 q2 q3 L H h l X h X q1 q2 q3 H Shift Right Parallel Load L L L H l h l X X L q0 q1 q2 H l h h X X H q0 q1 q2 H h h X X pn p0 p1 p2 p3 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level pn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min VOH Output HIGH 2.0 Units VIH 10% VCC 2.5 5% VCC 2.7 Voltage V Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA VOL Output LOW Voltage IIH Input HIGH Current 5.0 µA Max VIN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µA Max VIN = 7.0V ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC VID Input Leakage V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V 46 mA Max Test IOD 10% VCC Conditions Recognized as a HIGH Signal 0.5 4.75 Output Leakage Circuit Current IIL Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current −60 33 3 IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded www.fairchildsemi.com 74F194 Absolute Maximum Ratings(Note 1) 74F194 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Shift Frequency 105 150 tPLH Propagation Delay 3.5 5.2 7.0 3.0 8.5 3.5 8.0 tPHL CP to Qn 3.5 5.5 7.0 3.0 8.5 3.5 8.0 tPHL Propagation Delay 4.5 8.6 12.0 4.5 14.5 4.5 14.0 MR to Qn Max Min Max 90 Min Units Max 90 MHz ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.0 6.0 4.0 tS(L) Pn or DSR or DSL to CP 4.0 4.0 4.0 tH(H) Hold Time, HIGH or LOW 1.0 1.5 1.0 tH(L) Pn or DSR or DSL to CP 0 1.0 1.0 tS(H) Setup Time, HIGH or LOW 10.0 10.5 11.0 tS(L) Sn to CP 8.0 8.0 8.0 tH(H) Hold Time, HIGH or LOW 0 0 0 Units Max ns ns tH(L) Sn to CP 0 0 0 tW(H) CP Pulse Width, HIGH 5.0 5.5 5.5 ns tW(L) MR Pulse Width, LOW 5.0 5.0 5.0 ns tREC Recovery Time MR to CP 9.0 9.0 11.0 ns www.fairchildsemi.com 4 74F194 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com 74F194 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6