74F273PC

Revised September 2000 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. ■ Ideal buffer for MOS microprocessor or memory The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. ■ Eight edge-triggered D-type flip-flops ■ Buffered common clock ■ Buffered, asynchronous Master Reset ■ See 74F377 for clock enable version ■ See 74F373 for transparent latch version ■ See 74F374 for 3-STATE version Ordering Code: Order Number Package Number Package Description 74F273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009511 www.fairchildsemi.com 74F273 Octal D-Type Flip-Flop April 1988 74F273 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description D0–D7 Data Inputs 1.0/1.0 20 µA/−0.6 mA MR Master Reset (Active LOW) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA Q0–Q7 Data Outputs 50/33.3 −1 mA/20 mA Mode Select-Function Table Inputs Output Operating Mode MR CP Dn Qn Reset (Clear) L X X L Load “1” H h H Load “0” H l L H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial = LOW-to-HIGH clock transition    Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA V Min IOH = −1 mA V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V mA Max Output HIGH Voltage VOL Output LOW Voltage IIH 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage VOH 2.0 Units VIH 10% VCC 0.5 5% VCC 0.5 Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current IIL Input LOW Current IOS Output Short-Circuit Current ICCH Power Supply Current −60 44 ICCL 56 3 Recognized as a HIGH Signal Recognized as a LOW Signal IID = 1.9 µA All other pins grounded VIOD = 150 mV All other pins grounded CP =  Dn = MR = HIGH www.fairchildsemi.com 74F273 Absolute Maximum Ratings(Note 1) 74F273 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = 5.0V VCC = 5.0V CL = 50 pF CL = 50 pF CL = 50 pF Typ Max Min Max 95 Min Units Max fMAX Maximum Clock Frequency 160 130 tPLH Propagation Delay 3.0 7.0 2.5 9.5 2.5 7.5 MHz tPHL Clock to Output 4.0 9.00 3.0 11.0 3.5 9.0 tPLH Propagation Delay tPHL MR to Output 4.5 9.5 3.0 11.0 4.0 10.0 ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = 5.0V Min Max Min Max TA = 0°C to +70°C VCC = 5.0V Min tS(H) Setup Time, HIGH or LOW 3.0 3.5 3.0 tS(L) Data to CP 3.5 4.0 3.5 tH(H) Hold Time, HIGH or LOW 0.5 1.0 0.5 tH(L) Data to CP 1.0 1.0 1.0 tW(L) MR Pulse Width, LOW 6.0 4.0 6.0 tW(H) CP Pulse Width 6.0 5.0 6.0 tW(L) HIGH or LOW 6.0 5.0 6.0 tREC Recovery Time, MR to CP 3.0 4.5 3.5 www.fairchildsemi.com 4 Units Max ns ns ns ns 74F273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74F273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74F273 Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com