Revised August 1999
74F537
1-of-10 Decoder with 3-STATE Outputs
General Description
The 74F537 is one-of-ten decoder/demultiplexer with four
active HIGH BCD inputs and ten mutually exclusive outputs. A polarity control input determines whether the outputs are active LOW or active HIGH. The 74F537 has 3STATE outputs, and a HIGH signal on the Output Enable
(OE) input forces all outputs to the high impedance state.
Two input enables, active HIGH E2 and active LOW E1, are
available for demultiplexing data to the selected output in
either non-inverted or inverted form. Input codes greater
than BCD nine cause all outputs to go to the inactive state
(i.e., same polarity as the P input).
Ordering Code:
Order Number
Package Number
Package Description
74F537SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F537PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009550
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74F537 1-of-10 Decoder with 3-STATE Outputs
April 1988
74F537
Unit Loading/Fan Out
Pin Names
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
20 µA/−0.6 mA
Description
A0–A3
Address Inputs
1.0/1.0
E1
Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
E2
Enable Input (Active HIGH)
1.0/1.0
20 µA/−0.6 mA
OE
Output Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
P
Polarity Control Input
1.0/1.0
20 µA/−0.6 mA
O0–O9
3-STATE Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Truth Table
Inputs
Function
OE E1
E2
Outputs
A3 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
High Impedance
H
X
X
X
X
X
X
Disable
L
H
X
X
X
X
X
L
X
L
X
X
X
X
Active HIGH
L
L
H
L
L
L
L
H
L
L
L
L
L
L
Output
L
L
H
L
L
L
H
L
H
L
L
L
L
L
(P = L)
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
L
L
L
L
L
H
L
H
H
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
H
L
L
L
H
H
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
Active LOW
L
L
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
Output
L
L
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
(P = H)
L
L
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
L
H
H
H
H
L
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
X
X
H
H
H
H
H
H
H
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
Outputs Equal P Input
74F537
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F537
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
twice the rated IOL (mA)
in LOW State (Max)
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
VOH
Output HIGH
Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IBVI
Input HIGH Current
2.0
Units
VIH
10% VCC
2.5
10% VCC
2.4
5% VCC
2.7
5% VCC
2.7
Output HIGH
Input Leakage
Test
IOD
Recognized as a LOW Signal
Min
IIN = −18 mA
IOH = −3 mA
V
Min
0.5
V
Min
IOL = 24 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
VIN = 0.5V
50
µA
Max
VOUT = 2.7V
−50
µA
Max
VOUT = 0.5V
−150
mA
Max
VOUT = 0V
IOH = −1 mA
IOH = −3 mA
10% VCC
Leakage Current
VID
Conditions
Recognized as a HIGH Signal
IOH = −1 mA
Breakdown Test
ICEX
VCC
V
4.75
Output Leakage
Circuit Current
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
All Other Pins Grounded
IIL
Input LOW Current
IOZH
Output Leakage Current
IOZL
Output Leakage Current
IOS
Output Short-Circuit Current
IZZ
Bus Drainage Test
500
µA
0.0V
VOUT = 5.25V
ICCH
Power Supply Current
56
mA
Max
VO = HIGH
ICCZ
Power Supply Current
66
mA
Max
VO = HIGH Z
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−60
44
4
74F537
AC Electrical Characteristics
Symbol
Parameter
tPLH
Propagation Delay
TA = +25°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
6.0
11.0
16.0
6.0
17.0
tPHL
An to On
4.0
7.5
11.0
4.0
12.0
tPLH
Propagation Delay
5.0
8.5
14.5
5.0
15.5
Units
ns
tPHL
E1 to On
4.0
6.5
9.0
4.0
10.0
tPLH
Propagation Delay
6.0
11.0
16.0
6.0
17.0
tPHL
E2 to On
5.0
10.0
14.0
5.0
15.0
tPLH
Propagation Delay
6.0
11.5
18.0
6.0
20.0
17.0
ns
tPHL
P to On
6.0
11.0
16.0
6.0
tPZH
Output Enable Time
3.0
5.5
10.5
3.0
11.5
tPZL
OE to On
5.0
9.0
13.0
5.0
14.0
tPHZ
Output Disable Time
2.0
4.0
6.0
2.0
7.0
tPLZ
OE to On
3.0
5.0
7.0
3.0
8.0
ns
5
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74F537
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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6
74F537 1-of-10 Decoder with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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