74F564PC

Revised October 2000 74F564 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The 74F564 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is sorted in the flip-flops on the LOW-to-HIGH Clock (CP) transition. ■ Inputs and outputs on opposite sides of package allow easy interface with microprocessors This device is functionally identical to the 74F574, but has inverted outputs. ■ Useful as input or output port for microprocessors ■ Functionally identical to 74F574 ■ 3-STATE outputs for bus-oriented applications Ordering Code: Order Number Package Number Package Description 74F564SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F564PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009563 www.fairchildsemi.com 74F564 Octal D-Type Flip-Flop with 3-STATE Outputs April 1983 74F564 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D0–D7 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA O0–O7 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Functional Description Function Table The 74F564 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Inputs Internal Outputs Function OE CP H H H H L L L L D Q O H L NC Z Hold     H NC Z Hold L H Z Load H L Z Load L H H Data Available H L L Data Available H L NC NC No Change in Data H H NC NC No Change in Data H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial  Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH VOL Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 Output LOW Voltage IIH 2.0 Units VIH V 10% VCC Input HIGH Input HIGH Current Output HIGH Leakage Current VID Input Leakage Test IOD Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCZ Power Supply Current IIN = −18 mA Min IOH = −3 mA IOH = −1 mA 0.5 V Min IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Recognized as a LOW Signal Min IOH = −3 mA Breakdown Test ICEX Conditions Recognized as a HIGH Signal IOH = −1 mA Current IBVI VCC V −60 55 3 IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 86 mA Max VO = HIGH Z www.fairchildsemi.com 74F564 Absolute Maximum Ratings(Note 1) 74F564 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Typ Max Min Max fMAX Maximum Clock Frequency 100 tPLH Propagation Delay 2.5 tPHL CP to On 2.5 5.9 8.5 2.5 8.5 tPZH Output Enable Time 3.0 5.6 9.0 2.5 10.0 3.0 6.2 9.0 2.5 10.0 Output Disable Time 1.5 3.4 5.5 1.5 6.5 1.5 2.7 5.5 1.5 6.5 tPZL tPHZ tPLZ 70 5.2 8.5 2.5 Units MHz 8.5 ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 2.0 2.0 tS(L) Dn to CP 2.5 2.5 tH(H) Hold Time, HIGH or LOW 2.0 2.0 tH(L) Dn to CP 2.0 2.0 tW(H) CP Pulse Width 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 www.fairchildsemi.com 4 Units Max ns ns 74F564 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74F564 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6