74F794PC

Revised February 2004 74F794 8-Bit Register with Readback General Description Features The 74F794 is an 8-bit register with readback capability designed to store data as well as read the register information back onto the data bus. The I/O bus (D bus) has 3-STATE outputs. Current sinking capability is 64 mA on both the D and Q busses. ■ 3-STATE outputs on the I/O port ■ D and Q output sink capability of 64 mA ■ Functionally and pin equivalent to the 74LS794 Data is loaded into the registers on the LOW-to-HIGH transition of the clock (CP). The output enable (OE) is used to enable data on D0–D7. When OE is LOW, the output of the registers is enabled on D0–D7, enabling D as an output bus. When OE is HIGH, D0–D7 are inputs to the registers configuring D as an input bus. Ordering Code: Order Number Package Number 74F794PC N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Logic Symbol © 2004 Fairchild Semiconductor Corporation Connection Diagram DS010652 www.fairchildsemi.com 74F794 8-Bit Register with Readback March 1990 74F794 Input Loading/Fan-Out Pin Names HIGH/LOW Description (U.L.) 20 µA/−0.6 mA 1.0/1.0 20 µA/−0.6 mA 3.5/1.083 70 µA/−650 µA Output Enable Input CP Clock Pulse Inputs D0–D7 D Bus Inputs/ 3-STATE Outputs 750/106.6 −15 mA/64 mA Q Bus Outputs 750/106.6 −15 mA/64 mA Q0–Q7 Truth Table Logic Diagram Inputs CP Current 1.0/1.0 OE Outputs OE Q D L or H or ↓ L Qn Output, Q L or H or ↓ H Qn Input ↑ L Qn Output, Q (Note 1) ↑ H D Input Note 1: In this case the output of the register is clocked to the inputs and the overall Q output is unchanged at Qn. www.fairchildsemi.com 2 Recommended Operating Conditions −65°C to + 150°C Storage Temperature Ambient Temperature under Bias −55° to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin 0°C to 70°C Free Air Ambient Temperature +4.5V to +5.5V Supply Voltage −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA ESD Last Passing Voltage (Min) 4000V Voltage Applied to Output In HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: In this case the output of the register is clocked to the inputs and the overall Q output is unchanged at Qn. Current Applied to Output in LOW State (Max) DC Electrical Characteristics Symbol Note 4: Either voltage limit or current limit is sufficient to protect inputs. Twice the Rated IOL (mA) Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Min over Operating Temperature Range unless otherwise specified Typ Max 2.0 Diode Voltage VOH VOL Output HIGH 2.4 2.8 Voltage 2.0 2.44 Output LOW 0.45 Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD IIL Input LOW IOS Output Short- Current Circuit Current IIH + Output Leakage IOZH Current IIL + Output Leakage IOZL Current VID Input Leakage Test IOD −100 Conditions Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal −1.2 V Min V Min 0.55 V Min IOL = 64 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V (OE, CP) 0.5 mA Max VIN = 5.5V (Dn) 50 µA Max VOUT = VCC V 0.0 µA 0.0 3.75 Circuit Current VCC V 4.75 Output Leakage Units IIN = −18 mA IOH = −3 mA IOH = −15 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V −0.6 mA −225 mA Max VOUT = 0V 70 µA Max VOUT = 2.7V Max (OE, CP) (Dn) −650 µA Max V 0.0 3.75 µA 0.0 4.75 Output Circuit Leakage Current VOUT = 0.5V (Dn) IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.25V ICCH Power Supply Current 65 mA Max VO = HIGH ICCL Power Supply Current 80 mA Max VO = LOW ICCZ Power Supply Current 80 mA Max VO = HIGH Z 3 www.fairchildsemi.com 74F794 Absolute Maximum Ratings(Note 2) 74F794 AC Electrical Characteristics Symbol Parameter Min fMAX Maximum Clock Frequency 90 tPLH Propagation Delay 2.5 tPHL CP to Qn tPZH Output Enable Time Output Disable Time 1.0 tPZL tPHZ tPLZ tS(H) Setup Time, HIGH or LOW tS(L) tH(H) TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Typ Max Min MHz 7.0 2.5 8.0 2.5 8.0 2.5 9.0 2.3 8.5 2.0 9.0 2.0 10.0 2.0 10.5 1.0 7.0 1.0 8.0 7.0 1.0 8.0 4.0 Bus to Clock 4.0 4.0 Hold Time, HIGH or LOW 1.5 1.5 tH(L) Bus to Clock 1.5 1.5 tW(H Clock Pulse Width 5.8 5.8 HIGH or LOW 5.8 5.8 www.fairchildsemi.com Max 90 4.0 4 Units ns ns ns ns ns ns 74F794 8-Bit Register with Readback Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com