74F825SC

Revised October 2000 74F825 8-Bit D-Type Flip-Flop General Description Features The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface. ■ 3-STATE output ■ Clock enable and clear ■ Multiple output enables Ordering Code: Order Number Package Number Package Description 74F825SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F825SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009597 www.fairchildsemi.com 74F825 8-Bit D-Type Flip-Flop April 1988 74F825 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description 1.0/1.0 20 µA/−0.6 mA 150/40 (33.3) −3 mA/24 mA (20 mA) 1.0/1.0 20 µA/−0.6 mA Clock Enable 1.0/1.0 20 µA/−0.6 mA Clear 1.0/1.0 20 µA/−0.6 mA Clock Input 1.0/2.0 20 µA/−1.2 mA D0–D7 Data Inputs O0–O7 3-STATE Data Outputs OE1, OE2, OE3 Output Enable Input EN CLR CP Functional Description Function Table The 74F825 consists of eight D-type edge-triggered flip-flops. This device has 3-STATE true outputs and is organized in broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The 74F825 has Clear (CLR) and Clock Enable (EN) pins. Inputs Internal Output Function OE CLR EN CP D When the CLR is LOW and the OE is LOW the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH the outputs do not change state, regardless of the data or clock input transitions. Q O H H L H X NC Z Hold H H L L X NC Z Hold H H H X X NC Z Hold L H H X X NC NC Hold H L X X X H Z Clear L L X H L Clear H H L L H Z Load H H L H L Z Load L H L L H L L H L     X L H L X L H L Data Available H L H Data Available H X NC NC No Change in Data L X NC NC No Change in Data L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial  Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH 2.0 Units VIH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL Output LOW Voltage IIH Input HIGH IBVI Input HIGH Current ICEX Output HIGH Leakage Current Test IOD Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Buss Drainage Test ICCZ Power Supply Current IIN = −18 mA IOH = −3 mA V Min 0.5 V Min IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Recognized as a LOW Signal Min IOH = −1 mA IOH = −3 mA 10% VCC Breakdown Test Input Leakage Conditions Recognized as a HIGH Signal IOH = −1 mA Current VID VCC V −60 75 3 IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 90 mA Max VO = HIGH Z www.fairchildsemi.com 74F825 Absolute Maximum Ratings(Note 1) 74F825 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 160 Max Min Max tPLH Propagation Delay 2.0 6.5 9.5 2.0 10.5 2.0 10.5 tPHL CP to On 2.0 6.6 9.5 2.0 10.5 2.0 10.5 tPHL Propagation Delay 60 Min Max 70 MHz 4.0 7.4 12.0 4.0 13.0 4.0 13.0 tPZH Output Enable Time 2.0 6.5 10.5 2.0 13.0 2.0 11.5 tPZL OE to On 2.0 6.6 10.5 2.0 13.0 2.0 11.5 tPHZ Output Disable TIme 1.5 3.5 7.0 1.0 7.5 1.5 7.5 tPLZ OE to On 1.5 3.3 7.0 1.0 7.5 1.5 7.5 CLR to On Units ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 2.5 4.0 3.0 tS(L) Dn to CP 2.5 4.0 3.0 tH(H) Hold Time, HIGH or LOW 2.5 2.5 2.5 tH(L) Dn to CP 2.5 2.5 2.5 tS(H) Setup Time, HIGH or LOW 4.5 5.0 5.0 tS(L) EN to CP 2.5 3.0 3.0 tH(H) Hold Time, HIGH or LOW 2.0 3.0 1.0 Units Max ns ns tH(L) EN to CP 0 2.0 0 tW(H) CP Pulse Width 5.0 6.0 6.0 tW(L) HIGH or LOW 5.0 6.0 6.0 tW(L) CLR Pulse Width, LOW 5.0 5.0 5.0 ns tREC CLR Recovery Time 5.0 5.0 5.0 ns www.fairchildsemi.com 4 ns 74F825 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F825 8-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6